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| REJ09B0310-0100 16 H8S/2125 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2125 R4F2125 R4P2125 Rev.1.00 Revision Date: Sep. 21, 2006 Rev. 1.00 Sep. 21, 2006 Page ii of xxxviii Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 1.00 Sep. 21, 2006 Page iii of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 1.00 Sep. 21, 2006 Page iv of xxxviii Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) Product code, Package dimensions, etc. The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 1.00 Sep. 21, 2006 Page v of xxxviii Preface The H8S/2125 Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU with Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU. This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit free running timer (FRT), a 16-bit cycle measurement timer (TCM), a 8-bit timer (TMR), watchdog timer (WDT), serial communication interface (SCI), I2C bus interface (IIC), an A/D converter, and I/O ports as on-chip peripheral modules required for system configuration. In addition, a data transfer controller (DTC) is included as bus master. A flash memory (F-ZTATTM*) or PROM (OTP Version) is available for this LSI's 512-Kbyte ROM. The CPU and ROM are connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This improves the instruction fetch and process speeds. Note: * F-ZTATTM is a trademark of Renesas Technology. Corp. Target Users: This manual was written for users who use the H8S/2125 in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2125 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read this manual in the order of the table of contents. This manual can be roughly categorized into the descriptions on the CPU, system control functions, peripheral functions and electrical characteristics. Rev. 1.00 Sep. 21, 2006 Page vi of xxxviii * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. * In order to understand the detailed function of a register whose name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 23, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g., serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2125 Group manuals: Document Title H8S/2125 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual Document No. This manual REJ09B0139 User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual Document No. REJ10B0058 ADE-702-282 REJ10B0024 REJ10B0026 Rev. 1.00 Sep. 21, 2006 Page vii of xxxviii Rev. 1.00 Sep. 21, 2006 Page viii of xxxviii Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 Overview............................................................................................................................... 1 Internal Block Diagram......................................................................................................... 3 Pin Description ..................................................................................................................... 4 1.3.1 Pin Assignments ................................................................................................... 4 1.3.2 Pin Functions in Each Operating Mode ................................................................ 7 1.3.3 Pin Functions ...................................................................................................... 11 Section 2 CPU......................................................................................................17 2.1 Features............................................................................................................................... 17 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ................................. 18 2.1.2 Differences from H8/300 CPU ........................................................................... 19 2.1.3 Differences from H8/300H CPU......................................................................... 19 CPU Operating Modes........................................................................................................ 20 2.2.1 Normal Mode...................................................................................................... 20 2.2.2 Advanced Mode.................................................................................................. 22 Address Space..................................................................................................................... 24 Register Configuration........................................................................................................ 25 2.4.1 General Registers................................................................................................ 26 2.4.2 Program Counter (PC) ........................................................................................ 27 2.4.3 Extended Control Register (EXR) ...................................................................... 27 2.4.4 Condition-Code Register (CCR)......................................................................... 28 2.4.5 Initial Register Values......................................................................................... 29 Data Formats....................................................................................................................... 30 2.5.1 General Register Data Formats ........................................................................... 30 2.5.2 Memory Data Formats ........................................................................................ 32 Instruction Set ..................................................................................................................... 33 2.6.1 Table of Instructions Classified by Function ...................................................... 34 2.6.2 Basic Instruction Formats ................................................................................... 45 Addressing Modes and Effective Address Calculation....................................................... 46 2.7.1 Register Direct--Rn ........................................................................................... 46 2.7.2 Register Indirect--@ERn ................................................................................... 46 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)............. 47 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn.............................................................. 47 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32................................... 47 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 1.00 Sep. 21, 2006 Page ix of xxxviii 2.8 2.9 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32................................................................ 48 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) .................................. 48 2.7.8 Memory Indirect--@@aa:8 ............................................................................... 49 2.7.9 Effective Address Calculation ............................................................................ 50 Processing States ................................................................................................................ 52 Usage Notes ........................................................................................................................ 54 2.9.1 Note on TAS Instruction Usage.......................................................................... 54 2.9.2 Note on STM/LDM Instruction Usage ............................................................... 54 2.9.3 Note on Bit Manipulation Instructions................................................................ 54 2.9.4 EEPMOV Instruction.......................................................................................... 55 Section 3 MCU Operating Modes ....................................................................... 57 3.1 3.2 Operating Mode Selection .................................................................................................. 57 Register Descriptions.......................................................................................................... 58 3.2.1 Mode Control Register (MDCR) ........................................................................ 58 3.2.2 System Control Register (SYSCR)..................................................................... 59 3.2.3 Serial Timer Control Register (STCR) ............................................................... 60 Operating Mode Descriptions ............................................................................................. 62 3.3.1 Mode 1................................................................................................................ 62 3.3.2 Mode 2................................................................................................................ 62 3.3.3 Mode 3................................................................................................................ 62 Pin Functions in Each Operating Mode .............................................................................. 63 Address Map....................................................................................................................... 64 3.3 3.4 3.5 Section 4 Exception Handling ............................................................................. 67 4.1 4.2 4.3 Exception Handling Types and Priority.............................................................................. 67 Exception Sources and Exception Vector Table................................................................. 68 Reset ................................................................................................................................... 69 4.3.1 Reset Exception Handling .................................................................................. 69 4.3.2 Interrupts Immediately after Reset...................................................................... 70 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ....................................... 70 Interrupt Exception Handling ............................................................................................. 71 Trap Instruction Exception Handling.................................................................................. 71 Stack Status after Exception Handling ............................................................................... 72 Usage Note ......................................................................................................................... 73 4.4 4.5 4.6 4.7 Section 5 Interrupt Controller.............................................................................. 75 5.1 5.2 5.3 Features............................................................................................................................... 75 Input/Output Pins................................................................................................................ 77 Register Descriptions.......................................................................................................... 77 Rev. 1.00 Sep. 21, 2006 Page x of xxxviii 5.4 5.5 5.6 5.7 5.8 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) .......................................... 78 5.3.2 Address Break Control Register (ABRKCR) ..................................................... 79 5.3.3 Break Address Registers A to C (BARA to BARC)........................................... 80 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL).................................................. 81 5.3.5 IRQ Enable Registers (IER)................................................................................ 82 5.3.6 IRQ Status Registers (ISR) ................................................................................. 82 Interrupt Sources................................................................................................................. 83 5.4.1 External Interrupt Sources .................................................................................. 83 5.4.2 Internal Interrupt Sources ................................................................................... 84 Interrupt Exception Handling Vector Tables ...................................................................... 85 Interrupt Control Modes and Interrupt Operation ............................................................... 87 5.6.1 Interrupt Control Mode 0 .................................................................................... 90 5.6.2 Interrupt Control Mode 1 .................................................................................... 92 5.6.3 Interrupt Exception Handling Sequence ............................................................. 95 5.6.4 Interrupt Response Times ................................................................................... 97 5.6.5 DTC Activation by Interrupt............................................................................... 98 Address Breaks ................................................................................................................. 100 5.7.1 Features............................................................................................................. 100 5.7.2 Block Diagram.................................................................................................. 100 5.7.3 Operation .......................................................................................................... 101 5.7.4 Usage Notes ...................................................................................................... 101 Usage Notes ...................................................................................................................... 103 5.8.1 Conflict between Interrupt Generation and Disabling ...................................... 103 5.8.2 Instructions for Disabling Interrupts ................................................................. 104 5.8.3 Interrupts during Execution of EEPMOV Instruction....................................... 104 5.8.4 External Interrupt Pin in Software Standby Mode and Watch Mode................ 104 5.8.5 Noise Canceller Switching................................................................................ 104 5.8.6 IRQ Status Register (ISR)................................................................................. 104 Section 6 Bus Controller (BSC).........................................................................105 6.1 6.2 6.3 Features............................................................................................................................. 105 Input/Output Pins.............................................................................................................. 106 Register Descriptions........................................................................................................ 107 6.3.1 Bus Control Register (BCR) ............................................................................. 107 6.3.2 Wait State Control Register (WSCR) ............................................................... 108 Bus Control....................................................................................................................... 110 6.4.1 Bus Specifications............................................................................................. 110 6.4.2 Advanced Mode................................................................................................ 111 6.4.3 Normal Mode.................................................................................................... 111 6.4.4 I/O Select Signals.............................................................................................. 112 Rev. 1.00 Sep. 21, 2006 Page xi of xxxviii 6.4 6.5 6.6 6.7 6.8 Basic Bus Interface ........................................................................................................... 113 6.5.1 Data Size and Data Alignment.......................................................................... 113 6.5.2 Valid Strobes .................................................................................................... 115 6.5.3 Basic Operation Timing.................................................................................... 116 6.5.4 Wait Control ..................................................................................................... 118 Burst ROM Interface ........................................................................................................ 120 6.6.1 Basic Operation Timing.................................................................................... 120 6.6.2 Wait Control ..................................................................................................... 121 Idle Cycle.......................................................................................................................... 121 Bus Arbitration ................................................................................................................. 123 6.8.1 Priority of Bus Masters ..................................................................................... 123 6.8.2 Bus Transfer Timing......................................................................................... 123 Section 7 Data Transfer Controller (DTC)........................................................ 125 7.1 7.2 Features............................................................................................................................. 126 Register Descriptions........................................................................................................ 127 7.2.1 DTC Mode Register A (MRA) ......................................................................... 128 7.2.2 DTC Mode Register B (MRB).......................................................................... 129 7.2.3 DTC Source Address Register (SAR)............................................................... 130 7.2.4 DTC Destination Address Register (DAR)....................................................... 130 7.2.5 DTC Transfer Count Register A (CRA) ........................................................... 130 7.2.6 DTC Transfer Count Register B (CRB)............................................................ 130 7.2.7 DTC Enable Registers (DTCER)...................................................................... 131 7.2.8 DTC Vector Register (DTVECR)..................................................................... 132 Activation Sources............................................................................................................ 133 Location of Register Information and DTC Vector Table ................................................ 134 Operation .......................................................................................................................... 136 7.5.1 Normal Mode.................................................................................................... 137 7.5.2 Repeat Mode..................................................................................................... 138 7.5.3 Block Transfer Mode ........................................................................................ 139 7.5.4 Chain Transfer .................................................................................................. 140 7.5.5 Interrupt Sources............................................................................................... 141 7.5.6 Operation Timing.............................................................................................. 141 7.5.7 Number of DTC Execution States .................................................................... 143 Procedures for Using DTC ............................................................................................... 144 7.6.1 Activation by Interrupt...................................................................................... 144 7.6.2 Activation by Software ..................................................................................... 144 Examples of Use of the DTC............................................................................................ 145 7.7.1 Normal Mode.................................................................................................... 145 7.7.2 Software Activation .......................................................................................... 146 7.3 7.4 7.5 7.6 7.7 Rev. 1.00 Sep. 21, 2006 Page xii of xxxviii 7.8 Usage Notes ...................................................................................................................... 147 7.8.1 Module Stop Mode Setting ............................................................................... 147 7.8.2 On-Chip RAM .................................................................................................. 147 7.8.3 DTCE Bit Setting.............................................................................................. 147 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode ....................... 147 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter .............. 147 Section 8 I/O Ports .............................................................................................149 8.1 Port 1................................................................................................................................. 152 8.1.1 Port 1 Data Direction Register (P1DDR).......................................................... 152 8.1.2 Port 1 Data Register (P1DR)............................................................................. 153 8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)............................................... 153 8.1.4 Pin Functions .................................................................................................... 154 8.1.5 Port 1 Input Pull-Up MOS ................................................................................ 155 Port 2................................................................................................................................. 156 8.2.1 Port 2 Data Direction Register (P2DDR).......................................................... 156 8.2.2 Port 2 Data Register (P2DR)............................................................................. 157 8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)............................................... 157 8.2.4 Pin Functions .................................................................................................... 158 8.2.5 Port 2 Input Pull-Up MOS ................................................................................ 161 Port 3................................................................................................................................. 162 8.3.1 Port 3 Data Direction Register (P3DDR).......................................................... 162 8.3.2 Port 3 Data Register (P3DR)............................................................................. 163 8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)............................................... 163 8.3.4 Pin Functions .................................................................................................... 164 8.3.5 Port 3 Input Pull-Up MOS ................................................................................ 164 Port 4................................................................................................................................. 165 8.4.1 Port 4 Data Direction Register (P4DDR).......................................................... 166 8.4.2 Port 4 Data Register (P4DR)............................................................................. 167 8.4.3 Port 4 Pull-Up MOS Control Register (P4PCR)............................................... 167 8.4.4 Port 4 Noise Canceller Enable Register (P4NCE) ............................................ 168 8.4.5 Port 4 Noise Canceller Mode Control Register (P4NCMC) ............................. 168 8.4.6 Port 4 Noise Cancel Cycle Setting Register (P4NCCS) ................................... 169 8.4.7 Pin Functions .................................................................................................... 169 Port 5................................................................................................................................. 172 8.5.1 Port 5 Data Direction Register (P5DDR).......................................................... 172 8.5.2 Port 5 Data Register (P5DR)............................................................................. 172 8.5.3 Pin Functions .................................................................................................... 173 Port 6................................................................................................................................. 174 8.6.1 Port 6 Data Direction Register (P6DDR).......................................................... 174 Rev. 1.00 Sep. 21, 2006 Page xiii of xxxviii 8.2 8.3 8.4 8.5 8.6 8.7 8.6.2 Port 6 Data Register (P6DR)............................................................................. 175 8.6.3 Port 6 Noise Canceller Enable Register (P6NCE) ............................................ 175 8.6.4 Port 6 Noise Canceller Mode Control Register (P6NCMC) ............................. 176 8.6.5 Port 6 Noise Cancel Cycle Setting Register (P6NCCS) ................................... 176 8.6.6 Pin Functions .................................................................................................... 178 Port 7................................................................................................................................. 181 8.7.1 Port 7 Input Data Register (P7PIN) .................................................................. 181 8.7.2 Pin Functions .................................................................................................... 181 Section 9 8-Bit PWM Timer (PWM) ................................................................ 183 9.1 9.2 9.3 Features............................................................................................................................. 183 Input/Output Pin ............................................................................................................... 185 Register Descriptions........................................................................................................ 185 9.3.1 PWM Register Select (PWSL).......................................................................... 186 9.3.2 PWM Data Registers (PWDR0 to PWDR15)................................................... 188 9.3.3 PWM Data Polarity Registers A and B (PWDPRA, PWDPRB) ...................... 189 9.3.4 PWM Output Enable Registers A and B (PWOERA, PWOERB).................... 190 9.3.5 Peripheral Clock Select Register (PCSR) ......................................................... 191 Operation .......................................................................................................................... 192 9.4.1 PWM Setting Example (Pulse Division System).............................................. 194 9.4.2 Diagram of PWM Used as D/A Converter ....................................................... 194 Usage Note ....................................................................................................................... 195 9.5.1 Module Stop Mode Setting ............................................................................... 195 9.4 9.5 Section 10 14-Bit PWM Timer (PWMX) ......................................................... 197 10.1 10.2 10.3 Features............................................................................................................................. 197 Input/Output Pins.............................................................................................................. 198 Register Descriptions........................................................................................................ 198 10.3.1 PWMX (D/A) Counter (DACNT) .................................................................... 199 10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB)...................... 200 10.3.3 PWMX (D/A) Control Register (DACR) ......................................................... 202 10.3.4 Peripheral Clock Select Register (PCSR) ......................................................... 203 Bus Master Interface......................................................................................................... 204 Operation .......................................................................................................................... 207 Usage Notes ...................................................................................................................... 214 10.6.1 Module Stop Mode Setting ............................................................................... 214 10.4 10.5 10.6 Section 11 16-Bit Free-Running Timer (FRT).................................................. 215 11.1 11.2 Features............................................................................................................................. 215 Input/Output Pins.............................................................................................................. 217 Rev. 1.00 Sep. 21, 2006 Page xiv of xxxviii 11.3 11.4 11.5 11.6 11.7 Register Descriptions........................................................................................................ 217 11.3.1 Free-Running Counter (FRC) ........................................................................... 218 11.3.2 Output Compare Registers A and B (OCRA and OCRB)................................. 218 11.3.3 Input Capture Registers A to D (ICRA to ICRD) ............................................. 218 11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) ...................... 219 11.3.5 Output Compare Register DM (OCRDM)........................................................ 219 11.3.6 Timer Interrupt Enable Register (TIER) ........................................................... 220 11.3.7 Timer Control/Status Register (TCSR)............................................................. 221 11.3.8 Timer Control Register (TCR).......................................................................... 224 11.3.9 Timer Output Compare Control Register (TOCR) ........................................... 225 Operation .......................................................................................................................... 227 11.4.1 Pulse Output...................................................................................................... 227 Operation Timing.............................................................................................................. 228 11.5.1 FRC Increment Timing ..................................................................................... 228 11.5.2 Output Compare Output Timing ....................................................................... 229 11.5.3 FRC Clear Timing ............................................................................................ 229 11.5.4 Input Capture Input Timing .............................................................................. 230 11.5.5 Buffered Input Capture Input Timing ............................................................... 231 11.5.6 Timing of Input Capture Flag (ICF) Setting ..................................................... 232 11.5.7 Timing of Output Compare Flag (OCF) setting................................................ 233 11.5.8 Timing of FRC Overflow Flag Setting ............................................................. 233 11.5.9 Automatic Addition Timing.............................................................................. 234 11.5.10 Mask Signal Generation Timing ....................................................................... 235 Interrupt Sources............................................................................................................... 236 Usage Notes ...................................................................................................................... 237 11.7.1 Conflict between FRC Write and Clear ............................................................ 237 11.7.2 Conflict between FRC Write and Increment..................................................... 238 11.7.3 Conflict between OCR Write and Compare-Match .......................................... 239 11.7.4 Switching of Internal Clock and FRC Operation .............................................. 240 11.7.5 Module Stop Mode Setting ............................................................................... 242 Section 12 16-Bit Cycle Measurement Timer (TCM) .......................................243 12.1 12.2 12.3 Features............................................................................................................................. 243 Input/Output Pins.............................................................................................................. 245 Register Descriptions........................................................................................................ 245 12.3.1 TCM Timer Counter (TCMCNT) ..................................................................... 246 12.3.2 TCM Cycle Limit Register (TCMMLCM) ....................................................... 246 12.3.3 TCM Input Capture Register (TCMICR).......................................................... 247 12.3.4 TCM Input Capture Buffer Register (TCMICRF) ............................................ 247 12.3.5 TCM Status Register (TCMCSR) ..................................................................... 247 Rev. 1.00 Sep. 21, 2006 Page xv of xxxviii 12.4 12.5 12.6 12.3.6 TCM Control Register (TCMCR)..................................................................... 249 12.3.7 TCM Interrupt Enable Register (TCMIER)...................................................... 251 Operation .......................................................................................................................... 253 12.4.1 Timer Mode ...................................................................................................... 253 12.4.2 Speed Measurement Mode................................................................................ 256 Interrupt Sources............................................................................................................... 262 Usage Notes ...................................................................................................................... 263 12.6.1 Conflict between TCMCNT Write and Count-Up Operation........................... 263 12.6.2 Conflict between TCMMLCM Write and Compare Match.............................. 263 12.6.3 Conflict between TCMICR Read and Input Capture........................................ 264 12.6.4 Conflict between Edge Detection in Speed Measurement Mode and Writing to TCMMLCM ............................................................................. 265 12.6.5 Conflict between Edge Detection in Speed Measurement Mode and Clearing of TCMMDS Bit in TCMCR....................................................... 266 12.6.6 Setting for Module Stop Mode ......................................................................... 266 Section 13 8-Bit Timer (TMR).......................................................................... 267 13.1 13.2 13.3 Features............................................................................................................................. 267 Input/Output Pins.............................................................................................................. 270 Register Descriptions........................................................................................................ 271 13.3.1 Timer Counter (TCNT)..................................................................................... 272 13.3.2 Time Constant Register A (TCORA)................................................................ 272 13.3.3 Time Constant Register B (TCORB) ................................................................ 272 13.3.4 Timer Control Register (TCR).......................................................................... 273 13.3.5 Timer Control/Status Register (TCSR)............................................................. 277 13.3.6 Time Constant Register C (TCORC) ................................................................ 282 13.3.7 Input Capture Registers R and F (TICRR and TICRF)..................................... 282 13.3.8 Timer Connection Register I (TCONRI) .......................................................... 283 13.3.9 Timer Connection Register S (TCONRS) ........................................................ 283 13.3.10 Timer XY Control Register (TCRXY) ............................................................. 284 Operation .......................................................................................................................... 285 13.4.1 Pulse Output...................................................................................................... 285 Operation Timing.............................................................................................................. 286 13.5.1 TCNT Count Timing ........................................................................................ 286 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................ 287 13.5.3 Timing of Timer Output at Compare-Match..................................................... 287 13.5.4 Timing of Counter Clear at Compare-Match.................................................... 288 13.5.5 TCNT External Reset Timing........................................................................... 288 13.5.6 Timing of Overflow Flag (OVF) Setting .......................................................... 289 TMR_0 and TMR_1 Cascaded Connection...................................................................... 290 13.4 13.5 13.6 Rev. 1.00 Sep. 21, 2006 Page xvi of xxxviii 13.7 13.8 13.9 13.6.1 16-Bit Count Mode ........................................................................................... 290 13.6.2 Compare-Match Count Mode ........................................................................... 290 TMR_Y and TMR_X Cascaded Connection .................................................................... 291 13.7.1 16-Bit Count Mode ........................................................................................... 291 13.7.2 Compare-Match Count Mode ........................................................................... 291 13.7.3 Input Capture Operation ................................................................................... 292 Interrupt Sources............................................................................................................... 294 Usage Notes ...................................................................................................................... 295 13.9.1 Conflict between TCNT Write and Counter Clear............................................ 295 13.9.2 Conflict between TCNT Write and Count-Up .................................................. 296 13.9.3 Conflict between TCOR Write and Compare-Match........................................ 297 13.9.4 Conflict between Compare-Matches A and B .................................................. 298 13.9.5 Switching of Internal Clocks and TCNT Operation.......................................... 298 13.9.6 Mode Setting with Cascaded Connection ......................................................... 300 13.9.7 Module Stop Mode Setting ............................................................................... 300 Section 14 Watchdog Timer (WDT)..................................................................301 14.1 14.2 14.3 Features............................................................................................................................. 301 Input/Output Pins.............................................................................................................. 303 Register Descriptions........................................................................................................ 303 14.3.1 Timer Counter (TCNT)..................................................................................... 303 14.3.2 Timer Control/Status Register (TCSR)............................................................. 304 Operation .......................................................................................................................... 308 14.4.1 Watchdog Timer Mode ..................................................................................... 308 14.4.2 Interval Timer Mode ......................................................................................... 310 Interrupt Sources............................................................................................................... 311 Usage Notes ...................................................................................................................... 312 14.6.1 Notes on Register Access.................................................................................. 312 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 313 14.6.3 Changing Values of CKS2 to CKS0 Bits.......................................................... 314 14.6.4 Changing Value of PSS Bit............................................................................... 314 14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode............. 314 14.4 14.5 14.6 Section 15 Serial Communication Interface (SCI) ............................................315 15.1 15.2 15.3 Features............................................................................................................................. 315 Input/Output Pins.............................................................................................................. 317 Register Descriptions........................................................................................................ 317 15.3.1 Receive Shift Register (RSR) ........................................................................... 318 15.3.2 Receive Data Register (RDR) ........................................................................... 318 15.3.3 Transmit Data Register (TDR).......................................................................... 318 Rev. 1.00 Sep. 21, 2006 Page xvii of xxxviii 15.4 15.5 15.6 15.7 15.8 15.3.4 Transmit Shift Register (TSR) .......................................................................... 318 15.3.5 Serial Mode Register (SMR) ............................................................................ 319 15.3.6 Serial Control Register (SCR) .......................................................................... 320 15.3.7 Serial Status Register (SSR) ............................................................................. 322 15.3.8 Serial Interface Mode Register (SCMR)........................................................... 324 15.3.9 Bit Rate Register (BRR) ................................................................................... 325 Operation in Asynchronous Mode .................................................................................... 331 15.4.1 Data Transfer Format........................................................................................ 332 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................... 333 15.4.3 Clock................................................................................................................. 334 15.4.4 SCI Initialization (Asynchronous Mode).......................................................... 335 15.4.5 Data Transmission (Asynchronous Mode) ....................................................... 336 15.4.6 Serial Data Reception (Asynchronous Mode) .................................................. 338 Multiprocessor Communication Function ........................................................................ 342 15.5.1 Multiprocessor Serial Data Transmission ......................................................... 343 15.5.2 Multiprocessor Serial Data Reception .............................................................. 345 Operation in Clocked Synchronous Mode ........................................................................ 348 15.6.1 Clock................................................................................................................. 348 15.6.2 SCI Initialization (Clocked Synchronous Mode).............................................. 349 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ................................. 350 15.6.4 Serial Data Reception (Clocked Synchronous Mode) ...................................... 353 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)........................................................................... 355 Interrupt Sources............................................................................................................... 357 Usage Notes ...................................................................................................................... 358 15.8.1 Module Stop Mode Setting ............................................................................... 358 15.8.2 Break Detection and Processing ....................................................................... 358 15.8.3 Mark State and Break Detection ....................................................................... 358 15.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only).................................................................. 358 15.8.5 Relation between Writing to TDR and TDRE Flag .......................................... 358 15.8.6 Restrictions on Using DTC............................................................................... 359 15.8.7 SCI Operations during Mode Transitions ......................................................... 359 15.8.8 Notes on Switching from SCK Pins to Port Pins .............................................. 363 15.8.9 Notes on Register Writing during the Receive, Transmit, or Transfer Operation........................................................................................ 364 Rev. 1.00 Sep. 21, 2006 Page xviii of xxxviii Section 16 I2C Bus Interface (IIC) .....................................................................365 16.1 16.2 16.3 Features............................................................................................................................. 365 Input/Output Pins.............................................................................................................. 367 Register Descriptions........................................................................................................ 368 16.3.1 I2C Bus Data Register (ICDR) .......................................................................... 368 16.3.2 Slave Address Register (SAR).......................................................................... 369 16.3.3 Second Slave Address Register (SARX) .......................................................... 370 16.3.4 I2C Bus Mode Register (ICMR)........................................................................ 372 16.3.5 I2C Bus Control Register (ICCR)...................................................................... 375 16.3.6 I2C Bus Status Register (ICSR)......................................................................... 384 16.3.7 DDC Switch Register (DDCSWR) ................................................................... 389 16.3.8 I2C Bus Extended Control Register (ICXR)...................................................... 390 Operation .......................................................................................................................... 394 16.4.1 I2C Bus Data Format ......................................................................................... 394 16.4.2 Initialization ...................................................................................................... 396 16.4.3 Master Transmit Operation ............................................................................... 396 16.4.4 Master Receive Operation................................................................................. 400 16.4.5 Slave Receive Operation................................................................................... 409 16.4.6 Slave Transmit Operation ................................................................................. 416 16.4.7 IRIC Setting Timing and SCL Control ............................................................. 419 16.4.8 Operation Using DTC ....................................................................................... 421 16.4.9 Noise Canceller................................................................................................. 423 16.4.10 Initialization of Internal State ........................................................................... 423 Interrupt Sources............................................................................................................... 425 Usage Notes ...................................................................................................................... 425 16.6.1 Note on Wait Function in Master Mode ........................................................... 437 16.6.2 Module Stop Mode Setting ............................................................................... 437 16.4 16.5 16.6 Section 17 A/D Converter..................................................................................439 17.1 17.2 17.3 Features............................................................................................................................. 439 Input/Output Pins.............................................................................................................. 441 Register Descriptions........................................................................................................ 442 17.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 442 17.3.2 A/D Control/Status Register (ADCSR) ............................................................ 443 17.3.3 A/D Control Register (ADCR) ......................................................................... 444 Operation .......................................................................................................................... 445 17.4.1 Single Mode...................................................................................................... 445 17.4.2 Scan Mode ........................................................................................................ 445 17.4.3 Input Sampling and A/D Conversion Time ...................................................... 446 Rev. 1.00 Sep. 21, 2006 Page xix of xxxviii 17.4 17.5 17.6 17.7 17.4.4 External Trigger Input Timing.......................................................................... 448 Interrupt Source ................................................................................................................ 449 A/D Conversion Accuracy Definitions ............................................................................. 449 Usage Notes ...................................................................................................................... 451 17.7.1 Permissible Signal Source Impedance .............................................................. 451 17.7.2 Influences on Absolute Accuracy ..................................................................... 451 17.7.3 Setting Range of Analog Power Supply and Other Pins................................... 452 17.7.4 Notes on Board Design ..................................................................................... 452 17.7.5 Notes on Noise Countermeasures ..................................................................... 452 17.7.6 Module Stop Mode Setting ............................................................................... 453 Section 18 RAM ................................................................................................ 455 Section 19 Flash Memory (0.18-m F-ZTAT Version).................................... 457 19.1 Features............................................................................................................................. 457 19.1.1 Mode Transitions .............................................................................................. 459 19.1.2 Mode Comparison ............................................................................................ 460 19.1.3 Flash Memory MAT Configuration.................................................................. 461 19.1.4 Block Division .................................................................................................. 461 19.1.5 Programming/Erasing Interface ........................................................................ 464 Input/Output Pins.............................................................................................................. 466 Register Descriptions........................................................................................................ 467 19.3.1 Programming/Erasing Interface Registers ........................................................ 468 19.3.2 Programming/Erasing Interface Parameters ..................................................... 475 On-Board Programming ................................................................................................... 486 19.4.1 Boot Mode ........................................................................................................ 486 19.4.2 User Program Mode.......................................................................................... 490 19.4.3 User Boot Mode................................................................................................ 501 19.4.4 Storable Areas for Procedure Program and Program Data ............................... 505 Protection.......................................................................................................................... 514 19.5.1 Hardware Protection ......................................................................................... 514 19.5.2 Software Protection........................................................................................... 515 19.5.3 Error Protection ................................................................................................ 515 Switching between User MAT and User Boot MAT........................................................ 517 Programmer Mode ............................................................................................................ 518 Serial Communication Interface Specifications for Boot Mode ....................................... 519 Usage Notes ...................................................................................................................... 546 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 Rev. 1.00 Sep. 21, 2006 Page xx of xxxviii Section 20 PROM (OTP Version) .....................................................................549 20.1 Programmer Mode ............................................................................................................ 550 20.1.1 Programmer Mode Setting................................................................................ 550 20.1.2 Socket Adapters and Memory Map .................................................................. 550 Usage Notes ...................................................................................................................... 551 20.2 Section 21 Clock Pulse Generator .....................................................................553 21.1 Oscillator........................................................................................................................... 554 21.1.1 Connecting Crystal Resonator .......................................................................... 554 21.1.2 External Clock Input Method............................................................................ 555 Duty Correction Circuit .................................................................................................... 558 Medium-Speed Clock Divider .......................................................................................... 558 Bus Master Clock Select Circuit....................................................................................... 558 Subclock Input Circuit ...................................................................................................... 559 Subclock Waveform Forming Circuit............................................................................... 560 Clock Select Circuit .......................................................................................................... 560 Usage Notes ...................................................................................................................... 561 21.8.1 Notes on Resonator ........................................................................................... 561 21.8.2 Notes on Board Design ..................................................................................... 561 21.2 21.3 21.4 21.5 21.6 21.7 21.8 Section 22 Power-Down Modes ........................................................................563 22.1 Register Descriptions........................................................................................................ 564 22.1.1 Standby Control Register (SBYCR) ................................................................. 564 22.1.2 Low-Power Control Register (LPWRCR) ........................................................ 566 22.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, and MSTPCRB).................................. 568 22.2 Mode Transitions and LSI States ...................................................................................... 570 22.3 Medium-Speed Mode ....................................................................................................... 574 22.4 Sleep Mode ....................................................................................................................... 575 22.5 Software Standby Mode.................................................................................................... 576 22.6 Hardware Standby Mode .................................................................................................. 578 22.7 Watch Mode...................................................................................................................... 579 22.8 Subsleep Mode.................................................................................................................. 580 22.9 Subactive Mode ................................................................................................................ 581 22.10 Module Stop Mode ........................................................................................................... 582 22.11 Direct Transitions ............................................................................................................. 582 22.12 Usage Notes ...................................................................................................................... 583 22.12.1 I/O Port Status................................................................................................... 583 22.12.2 Current Consumption when Waiting for Oscillation Stabilization ................... 583 Rev. 1.00 Sep. 21, 2006 Page xxi of xxxviii 22.12.3 DTC Module Stop Mode .................................................................................. 583 Section 23 List of Registers............................................................................... 585 23.1 23.2 23.3 23.4 23.5 Register Addresses (Address Order)................................................................................. 586 Register Bits ..................................................................................................................... 593 Register States in Each Operating Mode .......................................................................... 599 Register Selection Condition ............................................................................................ 605 Register Addresses (Classification by Type of Module) .................................................. 611 Section 24 Electrical Characteristics ................................................................. 619 24.1 24.2 24.3 Absolute Maximum Ratings ............................................................................................. 619 DC Characteristics ............................................................................................................ 620 AC Characteristics ............................................................................................................ 624 24.3.1 Clock Timing .................................................................................................... 625 24.3.2 Control Signal Timing ...................................................................................... 627 24.3.3 Bus Timing ....................................................................................................... 629 24.3.4 Timing of On-Chip Peripheral Modules ........................................................... 635 A/D Conversion Characteristics ....................................................................................... 643 Flash Memory Characteristics .......................................................................................... 644 Usage Notes ...................................................................................................................... 645 24.4 24.5 24.6 Appendix ............................................................................................................. 647 A. B. C. I/O Port States in Each Processing State........................................................................... 647 Product Codes................................................................................................................... 649 Package Dimensions ......................................................................................................... 650 Index ................................................................................................................... 653 Rev. 1.00 Sep. 21, 2006 Page xxii of xxxviii Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Overview Block Diagram .............................................................................................................. 3 Pin Assignments (SDIP-64) .......................................................................................... 4 Pin Assignments (QFP-64)............................................................................................ 5 Pin Assignments (TQFP-80) ......................................................................................... 6 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 21 Figure 2.2 Stack Structure in Normal Mode ................................................................................. 21 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 22 Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 23 Figure 2.5 Memory Map............................................................................................................... 24 Figure 2.6 CPU Internal Registers ................................................................................................ 25 Figure 2.7 Usage of General Registers ......................................................................................... 26 Figure 2.8 Stack............................................................................................................................ 27 Figure 2.9 General Register Data Formats (1).............................................................................. 30 Figure 2.9 General Register Data Formats (2).............................................................................. 31 Figure 2.10 Memory Data Formats............................................................................................... 32 Figure 2.11 Instruction Formats (Examples) ................................................................................ 45 Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 49 Figure 2.13 State Transitions ........................................................................................................ 53 Section 3 MCU Operating Modes Figure 3.1 Address Map (1).......................................................................................................... 64 Figure 3.2 Address Map (2).......................................................................................................... 65 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Exception Handling Reset Sequence (Mode 2)............................................................................................ 70 Stack Status after Exception Handling ........................................................................ 72 Operation when SP Value Is Odd................................................................................ 73 Interrupt Controller Block Diagram of Interrupt Controller........................................................................ 76 Block Diagram of Interrupts IRQ7 to IRQ0 ................................................................ 84 Block Diagram of Interrupt Control Operation ........................................................... 88 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 91 State Transition in Interrupt Control Mode 1 .............................................................. 92 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1....... 94 Interrupt Exception Handling ...................................................................................... 96 Rev. 1.00 Sep. 21, 2006 Page xxiii of xxxviii Figure 5.8 Interrupt Control for DTC ........................................................................................... 98 Figure 5.9 Block Diagram of Address Break Function .............................................................. 100 Figure 5.10 Examples of Address Break Timing........................................................................ 102 Figure 5.11 Conflict between Interrupt Generation and Disabling............................................. 103 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller.............................................................................. 106 Figure 6.2 IOS Signal Output Timing ........................................................................................ 112 Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 113 Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 114 Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 116 Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 117 Figure 6.7 Example of Wait State Insertion Timing (Pin Wait Mode) ....................................... 119 Figure 6.8 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)...................... 120 Figure 6.9 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)...................... 121 Figure 6.10 Examples of Idle Cycle Operation .......................................................................... 122 Section 7 Data Transfer Controller (DTC) Figure 7.1 Block Diagram of DTC ............................................................................................. 126 Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 133 Figure 7.3 DTC Register Information Location in Address Space............................................. 134 Figure 7.4 DTC Operation Flowchart......................................................................................... 136 Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 137 Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 138 Figure 7.7 Memory Mapping in Block Transfer Mode .............................................................. 139 Figure 7.8 Chain Transfer Operation.......................................................................................... 140 Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 141 Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ...................................... 142 Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 142 Section 8 I/O Ports Figure 8.1 Noise Cancel Circuit ................................................................................................. 177 Figure 8.2 Conceptual Diagram of Noise Cancel Operation ...................................................... 177 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 8-Bit PWM Timer (PWM) Block Diagram of PWM Timer................................................................................. 184 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000).......... 193 Example of PWM Setting.......................................................................................... 194 Example when PWM is Used as D/A Converter....................................................... 194 Rev. 1.00 Sep. 21, 2006 Page xxiv of xxxviii Section 10 Figure 10.1 Figure 10.2 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 14-Bit PWM Timer (PWMX) PWMX (D/A) Block Diagram................................................................................. 197 (1) DACNT Access Operation (1) [CPU DACNT(H'AA57) Writing]............... 205 (2) DACNT Access Operation (2) [DACNT CPU(H'AA57) Reading].............. 206 PWMX (D/A) Operation ......................................................................................... 207 Output Waveform (OS = 0, DADR corresponds to TL) .......................................... 210 Output Waveform (OS = 1, DADR corresponds to TH) .......................................... 211 D/A Data Register Configuration when CFS = 1 .................................................... 211 Output Waveform when DADR = H'0207 (OS = 1) ............................................... 212 Section 11 16-Bit Free-Running Timer (FRT) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer ....................................................... 216 Figure 11.2 Example of Pulse Output......................................................................................... 227 Figure 11.3 Increment Timing with Internal Clock Source ........................................................ 228 Figure 11.4 Increment Timing with External Clock Source ....................................................... 228 Figure 11.5 Timing of Output Compare A Output ..................................................................... 229 Figure 11.6 Clearing of FRC by Compare-Match A Signal ....................................................... 229 Figure 11.7 Input Capture Input Signal Timing (Usual Case) .................................................... 230 Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)....................... 230 Figure 11.9 Buffered Input Capture Timing ............................................................................... 231 Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) ...................................................... 232 Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting .................. 232 Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................. 233 Figure 11.13 Timing of Overflow Flag (OVF) Setting............................................................... 234 Figure 11.14 OCRA Automatic Addition Timing ...................................................................... 234 Figure 11.15 Timing of Input Capture Mask Signal Setting....................................................... 235 Figure 11.16 Timing of Input Capture Mask Signal Clearing .................................................... 235 Figure 11.17 Conflict between FRC Write and Clear................................................................. 237 Figure 11.18 Conflict between FRC Write and Increment ......................................................... 238 Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used) ............................................... 239 Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) ...................................................... 240 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 16-Bit Cycle Measurement Timer (TCM) Block Diagram of the TCM..................................................................................... 244 Example of Free Running Counter Operation ......................................................... 253 Count Timing of External Clock Operation (Falling Edges)................................... 253 Input Capture Operation Timing (Sensing of Rising Edges)................................... 254 Buffer Operation of Input Capture .......................................................................... 254 Timing of CMF Flag Setting on a Compare Match................................................. 255 Rev. 1.00 Sep. 21, 2006 Page xxv of xxxviii Figure 12.7 Example of Counter Operation in Speed Measurement Mode ................................ 256 Figure 12.8 Example of Timing in Speed Measurement ............................................................ 257 Figure 12.9 Example of Timing in Fan-Stopped State (1).......................................................... 258 Figure 12.10 Example of Timing in Fan-Stopped State (2)........................................................ 258 Figure 12.11 Example of Speed Measurement Mode Settings ................................................... 259 Figure 12.12 Conflict between TCMCNT Write and Count-Up Operation ............................... 263 Figure 12.13 Conflict between TCMMLCM Write and Compare Match .................................. 263 Figure 12.14 Conflict between TCMICR Read and Input Capture ............................................ 264 Figure 12.15 Conflict between Edge Detection and Register Write (Speed Measurement Mode).................................................................................. 265 Figure 12.16 Conflict between Edge Detection and Clearing of TCMMDS (to Switch from Speed Measurement Mode to Timer Mode)................................ 266 Section 13 8-Bit Timer (TMR) Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 268 Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 269 Figure 13.3 Pulse Output Example ............................................................................................. 285 Figure 13.4 Count Timing for Internal Clock Input ................................................................... 286 Figure 13.5 Count Timing for External Clock Input (Both Edges) ............................................ 286 Figure 13.6 Timing of CMF Setting at Compare-Match ............................................................ 287 Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 287 Figure 13.8 Timing of Counter Clear by Compare-Match ......................................................... 288 Figure 13.9 Timing of Counter Clear by External Reset Input................................................... 288 Figure 13.10 Timing of OVF Flag Setting ................................................................................. 289 Figure 13.11 Timing of Input Capture Operation....................................................................... 292 Figure 13.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) ............................. 293 Figure 13.13 Conflict between TCNT Write and Clear.............................................................. 295 Figure 13.14 Conflict between TCNT Write and Count-Up ...................................................... 296 Figure 13.15 Conflict between TCOR Write and Compare-Match ............................................ 297 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Watchdog Timer (WDT) Block Diagram of WDT .......................................................................................... 302 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 309 Interval Timer Mode Operation............................................................................... 310 OVF Flag Set Timing .............................................................................................. 310 Writing to TCNT and TCSR (WDT_0)................................................................... 312 Conflict between TCNT Write and Increment ........................................................ 313 Rev. 1.00 Sep. 21, 2006 Page xxvi of xxxviii Section 15 Serial Communication Interface (SCI) Figure 15.1 Block Diagram of SCI............................................................................................. 316 Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 331 Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 333 Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ............................................................................................. 334 Figure 15.5 Sample SCI Initialization Flowchart ....................................................................... 335 Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 336 Figure 15.7 Sample Serial Transmission Flowchart ................................................................... 337 Figure 15.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 338 Figure 15.9 Sample Serial Reception Flowchart (1)................................................................... 340 Figure 15.9 Sample Serial Reception Flowchart (2)................................................................... 341 Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........................................... 343 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 344 Figure 15.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 345 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 346 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 347 Figure 15.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 348 Figure 15.15 Sample SCI Initialization Flowchart ..................................................................... 349 Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode................... 351 Figure 15.17 Sample Serial Transmission Flowchart ................................................................. 352 Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode .................... 353 Figure 15.19 Sample Serial Reception Flowchart ...................................................................... 354 Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 356 Figure 15.21 Example of Transmission using DTC in Clocked Synchronous Mode ................. 359 Figure 15.22 Sample Flowchart for Mode Transition during Transmission............................... 360 Figure 15.23 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 361 Figure 15.24 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock)...................................................................................................... 361 Figure 15.25 Sample Flowchart for Mode Transition during Reception .................................... 362 Figure 15.26 Switching from SCK Pins to Port Pins.................................................................. 363 Figure 15.27 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 363 Rev. 1.00 Sep. 21, 2006 Page xxvii of xxxviii Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9 I2C Bus Interface (IIC) Block Diagram of I2C Bus Interface ....................................................................... 366 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 367 I2C Bus Data Format (I2C Bus Format)................................................................... 394 I2C Bus Data Format (Serial Format) ...................................................................... 394 I2C Bus Timing........................................................................................................ 395 Sample Flowchart for IIC Initialization .................................................................. 396 Sample Flowchart for Operations in Master Transmit Mode .................................. 397 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ...... 399 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0)........................................................ 400 Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 401 Figure 16.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ............................................................................ 403 Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) .................................... 403 Figure 16.13 Sample Flowchart for Operations in Master Receive Mode (receiving multiple bytes) (WAIT = 1).................................................................. 404 Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (receiving a single byte) (WAIT = 1) .................................................................... 405 Figure 16.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) ............................................................................ 408 Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) ............................................................................ 408 Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 410 Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ... 412 Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ... 412 Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 413 Figure 16.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0)............................................................................ 415 Figure 16.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0)............................................................................ 415 Figure 16.23 Sample Flowchart for Slave Transmit Mode......................................................... 416 Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 418 Figure 16.25 IRIC Setting Timing and SCL Control (1) ............................................................ 419 Figure 16.26 IRIC Setting Timing and SCL Control (2) ............................................................ 420 Figure 16.27 IRIC Setting Timing and SCL Control (3) ............................................................ 421 Figure 16.28 Block Diagram of Noise Canceler......................................................................... 423 Figure 16.29 Notes on Reading Master Receive Data ................................................................ 430 Rev. 1.00 Sep. 21, 2006 Page xxviii of xxxviii Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing ............................................................................. 431 Figure 16.31 Stop Condition Issuance Timing ........................................................................... 432 Figure 16.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 433 Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 434 Figure 16.34 TRS Bit Set Timing in Slave Mode....................................................................... 435 Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost................................... 436 Figure 16.36 IRIC Flag Clear Timing in Wait Operation........................................................... 437 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Figure 17.8 A/D Converter Block Diagram of A/D Converter ........................................................................... 440 A/D Conversion Timing .......................................................................................... 447 External Trigger Input Timing ................................................................................ 448 A/D Conversion Accuracy Definitions.................................................................... 450 A/D Conversion Accuracy Definitions.................................................................... 450 Example of Analog Input Circuit ............................................................................ 451 Example of Analog Input Protection Circuit ........................................................... 453 Analog Input Pin Equivalent Circuit ....................................................................... 453 Section 19 Flash Memory (0.18-m F-ZTAT Version) Figure 19.1 Block Diagram of Flash Memory............................................................................ 458 Figure 19.2 Mode Transition for Flash Memory ........................................................................ 459 Figure 19.3 Flash Memory Configuration .................................................................................. 461 Figure 19.4 Block Division of User MAT (1) ............................................................................ 462 Figure 19.4 Block Division of User MAT (2) ............................................................................ 463 Figure 19.5 Overview of User Procedure Program..................................................................... 464 Figure 19.6 System Configuration in Boot Mode....................................................................... 487 Figure 19.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 487 Figure 19.8 Overview of Boot Mode State Transition Diagram................................................. 489 Figure 19.9 Programming/Erasing Overview Flow.................................................................... 490 Figure 19.10 RAM Map when Programming/Erasing is Executed ............................................ 491 Figure 19.11 Programming Procedure........................................................................................ 492 Figure 19.12 Erasing Procedure.................................................................................................. 498 Figure 19.13 Repeating Procedure of Erasing and Programming............................................... 500 Figure 19.14 Procedure for Programming User MAT in User Boot Mode ................................ 502 Figure 19.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 504 Figure 19.16 Transitions to Error-Protection State..................................................................... 516 Figure 19.17 Switching between User MAT and User Boot MAT ............................................ 517 Figure 19.18 Memory Map in Programmer Mode...................................................................... 518 Figure 19.19 Boot Program States .............................................................................................. 520 Figure 19.20 Bit-Rate-Adjustment Sequence ............................................................................. 521 Rev. 1.00 Sep. 21, 2006 Page xxix of xxxviii Figure 19.21 Figure 19.22 Figure 19.23 Figure 19.24 Communication Protocol Format .......................................................................... 522 Sequence of New Bit Rate Selection..................................................................... 533 Programming Sequence......................................................................................... 536 Erasure Sequence .................................................................................................. 540 Section 20 PROM (OTP Version) Figure 20.1 PROM Block Diagram (R4P2125).......................................................................... 549 Figure 20.2 Memory Map in Programmer Mode........................................................................ 550 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Figure 21.8 Figure 21.9 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................... 553 Typical Connection to Crystal Resonator................................................................ 554 Equivalent Circuit of Crystal Resonator.................................................................. 554 Example of External Clock Input ............................................................................ 555 External Clock Input Timing................................................................................... 556 Timing of External Clock Output Stabilization Delay Time................................... 557 Subclock Input from EXCL Pin .............................................................................. 559 Subclock Input Timing............................................................................................ 559 Note on Board Design of Oscillator Section ........................................................... 561 Power-Down Modes Mode Transition Diagram ....................................................................................... 571 Medium-Speed Mode Timing ................................................................................. 575 Software Standby Mode Application Example ....................................................... 577 Hardware Standby Mode Timing ............................................................................ 578 Section 24 Electrical Characteristics Figure 24.1 Darlington Transistor Drive Circuit (Example)....................................................... 623 Figure 24.2 LED Drive Circuit (Example) ................................................................................. 623 Figure 24.3 Output Load Circuit ................................................................................................ 624 Figure 24.4 System Clock Timing.............................................................................................. 625 Figure 24.5 Oscillation Stabilization Timing.............................................................................. 626 Figure 24.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 626 Figure 24.7 Reset Input Timing.................................................................................................. 627 Figure 24.8 Interrupt Input Timing............................................................................................. 628 Figure 24.9 Basic Bus Timing (Two-State Access).................................................................... 630 Figure 24.10 Basic Bus Timing (Three-State Access)................................................................ 631 Figure 24.11 Basic Bus Timing (Three-State Access with One Wait State) .............................. 632 Figure 24.12 Burst ROM Access Timing (Two-State Access)................................................... 633 Figure 24.13 Burst ROM Access Timing (One-State Access) ................................................... 634 Figure 24.14 I/O Port Input/Output Timing................................................................................ 636 Figure 24.15 FRT Input/Output Timing ..................................................................................... 636 Rev. 1.00 Sep. 21, 2006 Page xxx of xxxviii Figure 24.16 Figure 24.17 Figure 24.18 Figure 24.19 Figure 24.20 Figure 24.21 Figure 24.22 Figure 24.23 Figure 24.24 Figure 24.25 Figure 24.26 Figure 24.27 Figure 24.28 Figure 24.29 Figure 24.30 FRT Clock Input Timing ....................................................................................... 636 TCM Input/Output Timing .................................................................................... 637 TCM Clock Input Timing...................................................................................... 637 8-Bit Timer Output Timing ................................................................................... 637 8-Bit Timer Clock Input Timing ........................................................................... 637 8-Bit Timer Reset Input Timing ............................................................................ 638 PWM, PWMX Output Timing .............................................................................. 638 SCK Clock Input Timing....................................................................................... 638 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 638 A/D Converter External Trigger Input Timing...................................................... 639 I2C Bus Interface Input/Output Timing ................................................................. 640 ETCK Timing........................................................................................................ 641 Reset Hold Timing ................................................................................................ 642 H-UDI Input/Output Timing ................................................................................. 642 Connection of VCL Capacitor............................................................................... 645 Appendix Figure C.1 Package Dimensions (SDIP-64) ............................................................................... 650 Figure C.2 Package Dimensions (QFP-64)................................................................................. 651 Figure C.3 Package Dimensions (TQFP-80) .............................................................................. 652 Rev. 1.00 Sep. 21, 2006 Page xxxi of xxxviii Rev. 1.00 Sep. 21, 2006 Page xxxii of xxxviii Tables Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode .................................................................... 7 Table 1.2 Pin Functions .......................................................................................................... 11 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 33 Table 2.2 Operation Notation ................................................................................................. 34 Table 2.3 Data Transfer Instructions....................................................................................... 35 Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 36 Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 37 Table 2.5 Logic Operations Instructions................................................................................. 38 Table 2.6 Shift Instructions..................................................................................................... 39 Table 2.7 Bit Manipulation Instructions (1)............................................................................ 40 Table 2.7 Bit Manipulation Instructions (2)............................................................................ 41 Table 2.8 Branch Instructions ................................................................................................. 42 Table 2.9 System Control Instructions.................................................................................... 43 Table 2.10 Block Data Transfer Instructions ............................................................................ 44 Table 2.11 Addressing Modes .................................................................................................. 46 Table 2.12 Absolute Address Access Ranges ........................................................................... 48 Table 2.13 Effective Address Calculation (1)........................................................................... 50 Table 2.13 Effective Address Calculation (2)........................................................................... 51 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ............................................................................ 57 Table 3.2 Pin Functions in Each Mode ................................................................................... 63 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 67 Table 4.2 Exception Handling Vector Table........................................................................... 68 Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 71 Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 77 Table 5.2 Correspondence between Interrupt Source and ICR ............................................... 78 Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 85 Table 5.4 Interrupt Control Modes ......................................................................................... 87 Table 5.5 Interrupts Selected in Each Interrupt Control Mode ............................................... 89 Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode............ 90 Table 5.7 Interrupt Response Times ....................................................................................... 97 Rev. 1.00 Sep. 21, 2006 Page xxxiii of xxxviii Table 5.8 Table 5.9 Number of Execution States in Interrupt Handling Routine ................................... 97 Interrupt Source Selection and Clearing Control .................................................... 99 Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration.................................................................................................. 106 Table 6.2 Bus Specifications for Basic Bus Interface........................................................... 111 Table 6.3 Address Range for IOS Signal Output.................................................................. 112 Table 6.4 Data Buses Used and Valid Strobes...................................................................... 115 Table 6.5 Pin States in Idle Cycle......................................................................................... 122 Section 7 Data Transfer Controller (DTC) Table 7.1 Correspondence between Interrupt Sources and DTCER ..................................... 131 Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 135 Table 7.3 Register Functions in Normal Mode..................................................................... 137 Table 7.4 Register Functions in Repeat Mode...................................................................... 138 Table 7.5 Register Functions in Block Transfer Mode ......................................................... 139 Table 7.6 DTC Execution Status .......................................................................................... 143 Table 7.7 Number of States Required for Each Execution Status ........................................ 143 Section 8 I/O Ports Table 8.1 Port Functions....................................................................................................... 150 Table 8.2 Input Pull-Up MOS States (Port 1)....................................................................... 155 Table 8.3 Input Pull-Up MOS States (Port 2)....................................................................... 161 Table 8.4 Input Pull-Up MOS States (Port 3)....................................................................... 164 Section 9 8-Bit PWM Timer (PWM) Table 9.1 Pin Configuration.................................................................................................. 185 Table 9.2 Internal Clock Selection........................................................................................ 187 Table 9.3 Resolution, PWM Conversion Period and Carrier Frequency when = 20 MHz ................................................................................................. 188 Table 9.4 Duty Cycle of Basic Pulse .................................................................................... 192 Table 9.5 Position of Pulses Added to Basic Pulses ............................................................. 193 Section 10 14-Bit PWM Timer (PWMX) Table 10.1 Pin Configuration.................................................................................................. 198 Table 10.2 Clock Select of PWMX ........................................................................................ 203 Table 10.3 Reading/Writing to 16-bit Registers ..................................................................... 205 Table 10.4 Settings and Operation (Examples when = 20 MHz) ........................................ 208 Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 213 Section 11 16-Bit Free-Running Timer (FRT) Table 11.1 Pin Configuration.................................................................................................. 217 Table 11.2 FRT Interrupt Sources .......................................................................................... 236 Rev. 1.00 Sep. 21, 2006 Page xxxiv of xxxviii Table 11.3 Switching of Internal Clock and FRC Operation .................................................. 241 Section 12 16-Bit Cycle Measurement Timer (TCM) Table 12.1 Pin Configuration.................................................................................................. 245 Table 12.2 Range of Error in Measurement............................................................................ 260 Table 12.3 Range of Measurement Speed .............................................................................. 261 Table 12.4 TCM Interrupt Sources ......................................................................................... 262 Section 13 8-Bit Timer (TMR) Table 13.1 Pin Configuration.................................................................................................. 270 Table 13.2 Clock Input to TCNT and Count Condition (1) .................................................... 274 Table 13.2 Clock Input to TCNT and Count Condition (2) .................................................... 275 Table 13.3 Registers Accessible by TMR_X/TMR_Y ........................................................... 284 Table 13.4 Input Capture Signal Selection ............................................................................. 293 Table 13.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 294 Table 13.6 Timer Output Priorities ......................................................................................... 298 Table 13.7 Switching of Internal Clocks and TCNT Operation.............................................. 299 Section 14 Watchdog Timer (WDT) Table 14.1 Pin Configuration.................................................................................................. 303 Table 14.2 WDT Interrupt Source .......................................................................................... 311 Section 15 Serial Communication Interface (SCI) Table 15.1 Pin Configuration.................................................................................................. 317 Table 15.2 Relationships between N Setting in BRR and Bit Rate B..................................... 325 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode)................................. 326 Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 329 Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 329 Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 330 Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 330 Table 15.8 Serial Transfer Formats (Asynchronous Mode).................................................... 332 Table 15.9 SSR Status Flags and Receive Data Handling ...................................................... 339 Table 15.10 SCI Interrupt Sources........................................................................................ 357 Section 16 I2C Bus Interface (IIC) Table 16.1 Pin Configuration.................................................................................................. 367 Table 16.2 Communication Format ........................................................................................ 371 Table 16.3 I2C Transfer Rate .................................................................................................. 374 Table 16.4 Flags and Transfer States (Master Mode) ............................................................. 381 Table 16.5 Flags and Transfer States (Slave Mode) ............................................................... 382 Table 16.6 I2C Bus Data Format Symbols .............................................................................. 395 Table 16.7 Examples of Operation Using DTC ...................................................................... 422 Table 16.8 IIC Interrupt Sources ............................................................................................ 425 Rev. 1.00 Sep. 21, 2006 Page xxxv of xxxviii Table 16.9 Table 16.10 Table 16.11 I2C Bus Timing (SCL and SDA Outputs)............................................................. 426 Permissible SCL Rise Time (tsr) Values ........................................................... 427 I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 428 Section 17 A/D Converter Table 17.1 Pin Configuration.................................................................................................. 441 Table 17.2 Analog Input Channels and Corresponding ADDR.............................................. 442 Table 17.3 A/D Conversion Time (Single Mode)................................................................... 447 Table 17.4 A/D Converter Interrupt Source............................................................................ 449 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.1 Comparison of Programming Modes.................................................................... 460 Table 19.2 Pin Configuration.................................................................................................. 466 Table 19.3 Register/Parameter and Target Mode ................................................................... 468 Table 19.4 Parameters and Target Modes............................................................................... 476 Table 19.5 On-Board Programming Mode Setting ................................................................. 486 Table 19.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 488 Table 19.7 Executable MAT................................................................................................... 506 Table 19.8 (1) Usable Area for Programming in User Program Mode................................... 507 Table 19.8 (2) Usable Area for Erasure in User Program Mode............................................. 509 Table 19.8 (3) Usable Area for Programming in User Boot Mode......................................... 510 Table 19.8 (4) Usable Area for Erasure in User Boot Mode................................................... 512 Table 19.9 Hardware Protection ............................................................................................. 514 Table 19.10 Software Protection........................................................................................... 515 Table 19.11 Inquiry and Selection Commands..................................................................... 523 Table 19.12 Programming/Erasing Commands .................................................................... 535 Table 19.13 Status Code ....................................................................................................... 545 Table 19.14 Error Code ........................................................................................................ 545 Section 21 Clock Pulse Generator Table 21.1 Damping Resistor Values ..................................................................................... 554 Table 21.2 Crystal Resonator Parameters ............................................................................... 555 Table 21.3 External Clock Input Conditions .......................................................................... 556 Table 21.4 External Clock Output Stabilization Delay Time ................................................. 557 Table 21.5 Subclock Input Conditions.................................................................................... 559 Section 22 Power-Down Modes Table 22.1 Operating Frequency and Wait Time.................................................................... 566 Table 22.2 LSI Internal States in Each Operating Mode ........................................................ 572 Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings ................................................................................. 619 Table 24.2 DC Characteristics ................................................................................................ 620 Rev. 1.00 Sep. 21, 2006 Page xxxvi of xxxviii Table 24.3 Table 24.4 Table 24.5 Table 24.6 Table 24.7 Table 24.8 Table 24.9 Table 24.10 Table 24.11 Table 24.12 Appendix Table A.1 Permissible Output Currents ................................................................................. 622 Bus Drive Characteristics ..................................................................................... 622 Clock Timing ........................................................................................................ 625 Control Signal Timing .......................................................................................... 627 Bus Timing ........................................................................................................... 629 Timing of On-Chip Peripheral Modules ............................................................... 635 I2C Bus Timing ..................................................................................................... 639 H-UDI Timing .................................................................................................. 641 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) .............................................. 643 Flash Memory Characteristics .......................................................................... 644 I/O Port States in Each Processing State............................................................... 647 Rev. 1.00 Sep. 21, 2006 Page xxxvii of xxxviii Rev. 1.00 Sep. 21, 2006 Page xxxviii of xxxviii Section 1 Overview Section 1 Overview 1.1 Overview * 16-bit high-speed H8S/2000 CPU Upward-compatible with the H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions Data transfer controller (DTC) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit cycle measurement timer (TCM) 16-bit free-running timer (FRT) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) I2C bus interface (IIC) 10-bit A/D converter H-UDI interface (H-UDI) Clock pulse generator Rev. 1.00 Sep. 21, 2006 Page 1 of 658 REJ09B0310-0100 Section 1 Overview * On-chip memory ROM Type Flash memory version PROM (OTP version) Model R4F2125 R4P2125 ROM 512 Kbytes 512 Kbytes RAM 8 Kbytes 8 Kbytes Remarks Under development Under development * General I/O ports I/O pins: 43 Input pins: 8 * Supports various power-down states * Compact package Package SDIP-64 QFP-64 TQFP-80 Code PRDP0064BB-A (DP-64S) PRQP0064GB-A (FP-64A) PTQP0080KC-A (TFP-80C) Body Size 17.0 x 57.6 mm 14.0 x 14.0 mm 12.0 x 12.0 mm Pin Pitch 1.78 mm 0.8 mm 0.5 mm Rev. 1.00 Sep. 21, 2006 Page 2 of 658 REJ09B0310-0100 Section 1 Overview 1.2 Internal Block Diagram VCC VCL VSS VSS MD2* MD1 MD0 EXTAL XTAL STBY RES NMI P47/ WAIT/SDA0 P46/ /EXCL P45/ AS/ IOS P44/ WR P43/ RD P42/ IRQ0 P41/ IRQ1 P40/ IRQ2/ ADTRG Port 3 Port 2 Peripheral Address bus Internal address bus H8S/2000 CPU P37/ D7 P36/ D6 P35/ D5 P34/ D4 P33/ D3 P32/ D2 P31/ D1 P30/ D0 P27/ A15/ PW15/SCK1 P26/ A14/ PW14/RxD1 P25/ A13/ PW13/TxD1 P24/ A12/ PW12/ SCL1 P23/ A11/ PW11/ SDA1 P22/ A10/ PW10 P21/ A9/ PW9 P20/ A8/ PW8 Clock pulse generator Internal data bus Bus controller Interrupt controller DTC P67/ IRQ3/ TMOX/TMO1 P66/ FTOB/TMRI1 P65/ FTID/TMCI1 P64/ FTIC/TMO0 P63/ FTIB/TMRI0 P62/ FTIA/TMIY P61/ FTOA/TMOY P60/ FTCI/TMCI0/TMIX RAM 8-bit PWM 14-bit PWM 16-bit FRT SCI x 2 channels P77/ IRQ7/AN7/TCMCKI0 P76/ IRQ6/AN6/TCMCYI0 P75/ IRQ5/AN5/TCMCKI1 P74/ IRQ4/AN4/TCMCYI1 P73/ AN3 P72/ AN2 P71/ AN1 P70/ AN0 IIC x 2 channels 16-bit TCM x 2 channels 10-bit A/D Port 5 8-bit timer x 4 channels (TMR_0, TMR_1, TMR_X, TMR_Y) Port 1 Note: * Not supported in SDIP-64 and QFP-64. Port 4 ROM WDT0, WDT1 P17/ A7/ PW7 P16/ A6/ PW6 P15/ A5/ PW5 P14/ A4/ PW4 P13/ A3/ PW3 P12/ A2/ PW2 P11/ A1/ PW1/ PWX1 P10/ A0/ PW0/ PWX0 Port 6 Port 7 P52/ SCK0/ SCL0 P51/ RxD0 P50/ TxD0 H-UDI AVCC AVSS ETRST* ETMS* ETDO* ETDI* ETCK* Figure 1.1 Block Diagram Rev. 1.00 Sep. 21, 2006 Page 3 of 658 REJ09B0310-0100 Section 1 Overview 1.3 1.3.1 Pin Description Pin Assignments Figure 1.2 to 1.4 show the pin assignments of the H8S/2125 Group. P40/IRQ2/ADTRG P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS/IOS P46//EXCL P47/WAIT/SDA0 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 RES NMI VCL STBY VSS XTAL EXTAL MD1 MD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/IRQ4/AN4/TCMCYI1 P75/IRQ5/AN5/TCMCKI1 P76/IRQ6/AN6/TCMCYI0 P77/IRQ7/AN7/TCMCKI0 AVCC P60/FTCI/TMCI0/TMIX P61/FTOA/TMOY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SDIP-64 (Top view) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 P10/A0/PW0/PWX0 P11/A1/PW1/PWX1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 VSS P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 P23/A11/PW11/SDA1 P24/A12/PW12/SCL1 P25/A13/PW13/TxD1 P26/A14/PW14/RxD1 P27/A15/PW15/SCK1 VCC P67/IRQ3/TMOX/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA/TMIY Figure 1.2 Pin Assignments (SDIP-64) Rev. 1.00 Sep. 21, 2006 Page 4 of 658 REJ09B0310-0100 Section 1 Overview P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 P40/IRQ2/ADTRG P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS/IOS P46//EXCL P47/WAIT/SDA0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P10/A0/PW0/PWX0 P11/A1/PW1/PWX1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 VSS P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 P23/A11/PW11/SDA1 P24/A12/PW12/SCL1 P25/A13/PW13/TxD1 P26/A14/PW14/RxD1 QFP-64 (Top view) P27/ A15/ PW15/SCK1 VCC P67/ IRQ3/ TMOX/TMO1 P66/ FTOB/TMRI1 P65/ FTID/TMCI1 P64/ FTIC/TMO0 P63/ FTIB/TMRI0 P62/ FTIA/TMIY P61/ FTOA/TMOY P60/ FTCI/TMCI0/TMIX AVCC P77/ IRQ7/AN7/TCMCKI0 P76/ IRQ6/AN6/TCMCYI0 P75/ IRQ5/AN5/TCMCKI1 P74/ IRQ4/AN4/TCMCYI1 P73/ AN3 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 RES NMI VCL STBY VSS XTAL EXTAL MD1 MD0 AVSS P70/AN0 P71/AN1 P72/AN2 Figure 1.3 Pin Assignments (QFP-64) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Rev. 1.00 Sep. 21, 2006 Page 5 of 658 REJ09B0310-0100 Section 1 Overview P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 ETMS P35/D5 P36/D6 P37/D7 ETDO P40/IRQ2/ADTRG P41/IRQ1 ETDI P42/IRQ0 P43/RD ETCK P44/WR P45/AS/IOS P46//EXCL P47/WAIT/SDA0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P10/A0/PW0/PWX0 P11/A1/PW1/PWX1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 VSS P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 ETRST VSS VSS P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 VSS P23/A11/PW11/SDA1 P24/A12/PW12/SCL1 P25/A13/PW13/TxD1 P26/A14/PW14/RxD1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TQFP-80 (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P27/ A15/ PW15/SCK1 VCC P67/ IRQ3/ TMOX/TMO1 P66/ FTOB/TMRI1 P65/ FTID/TMCI1 P64/ FTIC/TMO0 VSS P63/ FTIB/TMRI0 P62/ FTIA/TMIY VSS P61/ FTOA/TMOY VSS P60/ FTCI/TMCI0/TMIX AVCC P77/ IRQ7/AN7/TCMCKI0 P76/ IRQ6/AN6/TCMCYI0 VSS P75/ IRQ5/AN5/TCMCKI1 P74/IRQ4/AN4/TCMCYI1 P73/ AN3 Rev. 1.00 Sep. 21, 2006 Page 6 of 658 REJ09B0310-0100 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 RES NMI VCL STBY MD2 VSS VSS XTAL VSS EXTAL MD1 VSS MD0 AVSS P70/AN0 P71/AN1 P72/AN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.4 Pin Assignments (TQFP-80) Section 1 Overview 1.3.2 Table 1.1 Pin Functions in Each Operating Mode Pin Functions in Each Operating Mode Pin Name Pin No. Mode 1 P40/IRQ2/ADTRG P41/IRQ1 ETDI P42/IRQ0 RD ETCK WR AS/IOS P46//EXCL P47/WAIT/SDA0 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 RES NMI VCL STBY MD2 VSS VSS XTAL VSS EXTAL MD1 VSS MD0 Extended Mode Mode 2 (EXPE = 1), Mode 3 (EXPE = 1) P40/IRQ2/ADTRG P41/IRQ1 ETDI P42/IRQ0 RD ETCK WR AS/IOS P46//EXCL P47/WAIT/SDA0 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 RES NMI VCL STBY MD2 VSS VSS XTAL VSS EXTAL MD1 VSS MD0 Single-Chip Mode Mode 2 (EXPE = 0), Mode 3 (EXPE = 0) P40/IRQ2/ADTRG P41/IRQ1 ETDI P42/IRQ0 P43 ETCK P44 P45 P46//EXCL P47/SDA0 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 RES NMI VCL STBY MD2 VSS VSS XTAL VSS EXTAL MD1 VSS MD0 Flash Memory Programmer Mode VCC VCC VCC VSS WE VCC FA15 FA16 VSS VCC FA19 FA17 FA18 RES FA9 VCL VCC VSS VSS VSS XTAL VSS EXTAL VSS VSS VSS SDIP-64 QFP-64 TQFP-80 1 2 3 4 5 6 7 8* 9 10 11* 12 13 14 15 16 17 18 19 20 57 58 59 60 61 62 63 64* 1 2 3* 4 5 6 7 8 9 10 11 12 71 72 73 74 75 76 77 78 79 80* 1 2 3* 4 5 6 7 8 9 10 11 12 13 14 15 16 Rev. 1.00 Sep. 21, 2006 Page 7 of 658 REJ09B0310-0100 Section 1 Overview Pin Name Pin No. Mode 1 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/IRQ4/AN4/ TCMCYI1 P75/IRQ5/AN5/ TCMCKI1 VSS P76/IRQ6/AN6/ TCMCYI0 P77/IRQ7/AN7/ TCMCKI0 AVCC P60/FTCI/TMCI0/ TMIX VSS P61/FTOA/TMOY VSS P62/FTIA/TMIY P63/FTIB/TMRI0 VSS P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/IRQ3/TMO1/ TMOX VCC A15 Extended Mode Mode 2 (EXPE = 1), Mode 3 (EXPE = 1) AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/IRQ4/AN4/ TCMCYI1 P75/IRQ5/AN5/ TCMCKI1 VSS P76/IRQ6/AN6/ TCMCYI0 P77/IRQ7/AN7/ TCMCKI0 AVCC P60/FTCI/TMCI0/ TMIX VSS P61/FTOA/TMOY VSS P62/FTIA/TMIY P63/FTIB/TMRI0 VSS P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/IRQ3/TMO1/ TMOX VCC P27/A15/PW15/ SCK1 Single-Chip Mode Mode 2 (EXPE = 0), Mode 3 (EXPE = 0) AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/IRQ4/AN4/ TCMCYI1 P75/IRQ5/AN5/ TCMCKI1 VSS P76/IRQ6/AN6/ TCMCYI0 P77/IRQ7/AN7/ TCMCKI0 AVCC P60/FTCI/TMCI0/ TMIX VSS P61/FTOA/TMOY VSS P62/FTIA/TMIY P63/FTIB/TMRI0 VSS P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/IRQ3/TMO1/ TMOX VCC P27/PW15/SCK1 Flash Memory Programmer Mode VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC CE SDIP-64 QFP-64 TQFP-80 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Rev. 1.00 Sep. 21, 2006 Page 8 of 658 REJ09B0310-0100 Section 1 Overview Pin Name Pin No. Mode 1 A14 A13 A12 A11 VSS A10 A9 A8 VSS VSS ETRST A7 A6 A5 VSS A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 ETMS Extended Mode Mode 2 (EXPE = 1), Mode 3 (EXPE = 1) P26/A14/PW14/ RxD1 P25/A13/PW13/ TxD1 P24/A12/PW12/ SCL1 P23/A11/PW11/ SDA1 VSS P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 VSS VSS ETRST P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 VSS P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1/PWX1 P10/A0/PW0/PWX0 D0 D1 D2 D3 D4 ETMS Single-Chip Mode Mode 2 (EXPE = 0), Mode 3 (EXPE = 0) P26/PW14/RxD1 P25/PW13/TxD1 P24/PW12/SCL1 P23/PW11/SDA1 VSS P22/PW10 P21/PW9 P20/PW8 VSS VSS ETRST P17/PW7 P16/PW6 P15/PW5 VSS P14/PW4 P13/PW3 P12/PW2 P11/PW1/PWX1 P10/PW0/PWX0 P30 P31 P32 P33 P34 ETMS Flash Memory Programmer Mode FA14 FA13 FA12 FA11 VSS FA10 OE FA8 VSS VSS VSS FA7 FA6 FA5 VSS FA4 FA3 FA2 FA1 FA0 FO0 FO1 FO2 FO3 FO4 VCC SDIP-64 QFP-64 TQFP-80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Rev. 1.00 Sep. 21, 2006 Page 9 of 658 REJ09B0310-0100 Section 1 Overview Pin Name Pin No. Mode 1 D5 D6 D7 ETDO Extended Mode Mode 2 (EXPE = 1), Mode 3 (EXPE = 1) D5 D6 D7 ETDO Single-Chip Mode Mode 2 (EXPE = 0), Mode 3 (EXPE = 0) P35 P36 P37 ETDO Flash Memory Programmer Mode FO5 FO6 FO7 NC SDIP-64 QFP-64 TQFP-80 62 63 64 54 55 56 67 68 69 70 Note: * NMOS push-pull/open-drain drive capability or 5-V tolerant input pin. Rev. 1.00 Sep. 21, 2006 Page 10 of 658 REJ09B0310-0100 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin No. Type Power supply Symbol VCC SDIP-64 QFP-64 TQFP-80 I/O Input Name and Function Power supply pin. Connect the pin to the system power supply. Connect the bypass capacitor between VCC and VSS (near VCC). External capacitance pin for internal step-down power. Connect this pin to VSS through an external capacitor (that is located near this pin) to stabilize internal step-down power. Ground pins. Connect all these pins to the system power supply (0 V). 39 31 39 VCL 14 6 6 Input VSS 16, 48 8, 40 9, 10, 12, 15, 24, 29, 31, 34, 45, 49, 50, 55 11 13 Input Clock XTAL EXTAL 17 18 9 10 Input Input For connection to a crystal resonator. An external clock can be supplied from the EXTAL pin. For an example of crystal resonator connection, see section 21, Clock Pulse Generator. EXCL Operating MD2*1 mode MD1 control MD0 7 7 19 20 63 63 11 12 79 79 8 14 16 Output Supplies the system clock to external devices. Input Input 32.768-kHz external sub-clock should be supplied. These pins set the operating mode. Inputs at these pins should not be changed during operation. Rev. 1.00 Sep. 21, 2006 Page 11 of 658 REJ09B0310-0100 Section 1 Overview Pin No. Type System control Symbol RES STBY Address bus A15 to A0 SDIP-64 QFP-64 TQFP-80 I/O Input Input Name and Function Reset pin. When this pin is low, the chip is reset. When this pin is low, a transition is made to hardware standby mode. 12 15 4 7 4 7 40 to 47, 32 to 39, 40 to 44, Output These pins output addresses. 49 to 56 41 to 48 46 to 48, 52 to 54, 56 to 60 64 to 57 56 to 49 69 to 67, Input/ These pins are bidirectional data 65 to 61 Output bus. 8 64 80 Input This pin requests insertion of a wait state in the bus cycle when accessing external 3-state address space. Data bus D7 to D0 Bus control WAIT RD 4 60 75 Output When this pin is low, it indicates that the external address space is being read. Output When this pin is low, it indicates that the external address space is being written to. Output When this pin is low, it indicates that address output on the address bus is valid. Input Input pin for a nonmaskable interrupt request. These pins request a maskable interrupt. WR 5 61 77 AS/IOS 6 62 78 Interrupts NMI IRQ0 to IRQ2, IRQ3, IRQ4 to IRQ7 PWM timer (PWM) 14-bit PWM timer (PWMX) PW15 to PW0 13 1 to 3 5 5 57 to 59 71, 72, Input 74 38 30 38 26 to 29 18 to 21 22 to 26 40 to 47, 32 to 39, 40 to 44, Output PWM timer pulse output pins. 49 to 56 41 to 48 46 to 48, 52 to 54, 56 to 60 56 55 48 47 60 59 Output PWMX pulse output pins PWX0 PWX1 Rev. 1.00 Sep. 21, 2006 Page 12 of 658 REJ09B0310-0100 Section 1 Overview Pin No. Type Symbol SDIP-64 QFP-64 TQFP-80 I/O Input Name and Function External event input pin. 16-bit free FTCI running FTOA timer FTOB (FRT) FTIA FTIB FTIC FTID 16-bit cycle measurement timer (TCM_0, TCM_1) 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y) TCMCKI0 TCMCKI1 TCMCYI0 TCMCYI1 31 32 37 33 34 25 36 29 27 28 26 23 24 29 25 26 27 28 21 19 20 18 28 30 37 32 33 35 36 26 23 25 22 Output Output compare output pins. Input Input capture input pins. Input Input Input pins for the external clock input to the counter. External event input pins. TMO0 TMO1 TMOX TMOY TMCI0 TMCI1 TMRI0 TMRI1 TMIX TMIY 35 38 38 32 31 36 34 37 31 33 9 42 10 41 11 40 27 30 30 24 23 28 26 29 23 25 1 34 2 33 3 32 35 38 38 30 28 36 33 37 28 32 1 42 2 41 3 40 Output Waveform output pins with output compare function. Input Input Input Input pins for the external clock input to the counter. Counter reset input pins. External event input pins and counter reset input pins. Serial communication interface (SCI_0, SCI_1) TxD0 TxD1 RxD0 RxD1 SCK0 SCK1 Output Transmit data output pins. Input Receive data input pins. Input/ Clock input/output pins. Output type Output is NMOS push-pull output. Input/ Clock input pin. Output Rev. 1.00 Sep. 21, 2006 Page 13 of 658 REJ09B0310-0100 Section 1 Overview Pin No. Type I C bus interface (IIC) 2 Symbol SCL0 SCL1 SDA0 SDA1 SDIP-64 QFP-64 TQFP-80 I/O Name and Function 11 43 8 44 3 35 64 36 3 43 80 44 Input/ I2C clock input/output pins. SCL0 Output output type is NMOS open drain and can drive a bus directly. Input/ I C data input/output pins. SDA0 Output output type is NMOS open drain and can drive a bus directly. Analog input pins External trigger input pin to start A/D conversion. Reference power supply for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+3 V). Ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Interface pins for emulator. 2 A/D AN7 to converter AN0 ADTRG AVCC 29 to 22 21 to 14 26, 25, Input 23 to 18 1 30 57 22 71 27 Input Input AVSS 21 13 17 Input H-UDI interface (H-UDI) ETRST*1*2 ETMS* ETDO* ETDI* 1 1 51 66 70 73 76 Input Input 1 ETCK* 1 Reset by holding the ETRST pin to low regardless of the H-UDI Output activation. At this time, the ETRST Input pin should be held low for 20 clocks of ETCK. Then, to activate the HInput UDI, the ETRST pin should be set to high and the pins ETCK, ETMS, and ETDI should be set appropriately. When in the normal operation without activating the HUDI, pins ETRST, ETCK, ETMS, and ETDI are set to high or highimpedance. As these pins are pulled up inside the chip, care is required during standby state. Rev. 1.00 Sep. 21, 2006 Page 14 of 658 REJ09B0310-0100 Section 1 Overview Pin No. Type I/O ports Symbol SDIP-64 QFP-64 TQFP-80 I/O Name and Function P17 to P10 49 to 56 41 to 48 52 to 54, Input/ 8-bit input/output pins. 56 to 60 Output P27 to P20 40 to 47 32 to 39 40 to 44, Input/ 8-bit input/output pins. 46 to 48 Output P37 to P30 64 to 57 56 to 49 69 to 67, Input/ 8-bit input/output pins. 65 to 61 Output P47 to P40 8 to 1 64 to 57 80 to 77, Input/ 8-bit input/output pins. 75 to 74, Output 72 to 71 3 to 1 3 to 1 Input/ 3-bit input/output pins. Output P52 to P50 11 to 9 P67 to P60 38 to 31 30 to 23 38 to 35, Input/ 8-bit input/output pins. 33 to 32, Output 30, 28 P77 to P70 29 to 22 21 to 14 26 to 25, Input 23 to 18 8-bit input pins. Notes: 1. Not supported in SDIP-64 and QFP-64. The input value on the MD2 or ETRST pin is fixed to 0. 2. Following precautions are required on the power-on reset signal that is applied to the ETRST pin. The reset signal should be applied on power supply. Set apart the power on reset circuit from this LSI to prevent the ETRST pin of the board tester from affecting the operation of this LSI. Set apart the power on reset circuit from this LSI to prevent the system reset of this LSI from affecting the ETRST pin of the board tester. Rev. 1.00 Sep. 21, 2006 Page 15 of 658 REJ09B0310-0100 Section 1 Overview Rev. 1.00 Sep. 21, 2006 Page 16 of 658 REJ09B0310-0100 Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16 Mbytes linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. 2.1 Features * Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 CPU and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16 Mbytes address space Program: 16 Mbytes Data: 16 Mbytes Rev. 1.00 Sep. 21, 2006 Page 17 of 658 REJ09B0310-0100 Section 2 CPU * High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 / 8-bit register-register divide: 12 states (DIVXU.B) 16 x 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 / 16-bit register-register divide: 20 states (DIVXU.W) * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. Rev. 1.00 Sep. 21, 2006 Page 18 of 658 REJ09B0310-0100 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. * Extended address space Normal mode supports the same 64 Kbytes address space as the H8/300 CPU. Advanced mode supports a maximum 16 Mbytes address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16 Mbytes address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. Rev. 1.00 Sep. 21, 2006 Page 19 of 658 REJ09B0310-0100 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64 Kbytes address space. Advanced mode supports a maximum 16 Mbytes address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. * Address space Linear access to a maximum address space of 64 Kbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.) * Instruction set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. Rev. 1.00 Sep. 21, 2006 Page 20 of 658 REJ09B0310-0100 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode Rev. 1.00 Sep. 21, 2006 Page 21 of 658 REJ09B0310-0100 Section 2 CPU 2.2.2 Advanced Mode * Address space Linear access to a maximum address space of 16 Mbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. * Instruction set All instructions and addressing modes can be used. * Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper eight bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 1.00 Sep. 21, 2006 Page 22 of 658 REJ09B0310-0100 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper eight bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. * Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. SP Reserved PC (24-bit) SP CCR PC (24-bit) (a) Subroutine Branch (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 1.00 Sep. 21, 2006 Page 23 of 658 REJ09B0310-0100 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64 Kbytes address space in normal mode, and a maximum 16 Mbytes (architecturally 4 Gbytes) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. H'0000 64 Kbytes H'FFFF H'00000000 16 Mbytes Program area H'00FFFFFF Data area Not available in this LSI H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in this LSI. Figure 2.5 Memory Map Rev. 1.00 Sep. 21, 2006 Page 24 of 658 REJ09B0310-0100 Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. These are classified into two types of registers: general registers and control registers. Control registers refer to a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers 23 PC 0 EXR* T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * Does not affect operation in this LSI. Figure 2.6 CPU Internal Registers Rev. 1.00 Sep. 21, 2006 Page 25 of 658 REJ09B0310-0100 Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing sixteen 16-bit registers at the maximum. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing sixteen 8-bit registers at the maximum. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 1.00 Sep. 21, 2006 Page 26 of 658 REJ09B0310-0100 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI. Bit 7 Initial Bit Name Value T 0 All 1 1 1 1 R/W R/W R R/W R/W R/W Description Trace Bit Does not affect operation in this LSI. 6 to 3 - 2 to 0 I2 I1 I0 Reserved These bits are always read as 1. Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI. Rev. 1.00 Sep. 21, 2006 Page 27 of 658 REJ09B0310-0100 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, see section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 when data is zero, and cleared to 0 when data is not zero. Rev. 1.00 Sep. 21, 2006 Page 28 of 658 REJ09B0310-0100 Section 2 CPU Bit 1 Bit Name V Initial Value Undefined R/W R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 1.00 Sep. 21, 2006 Page 29 of 658 REJ09B0310-0100 Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers. Data Type 1-bit data Register Number RnH Data Image 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 1.00 Sep. 21, 2006 Page 30 of 658 REJ09B0310-0100 Section 2 CPU Data Type Word data Register Number Rn Data Image 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB [Legend] ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 1.00 Sep. 21, 2006 Page 31 of 658 REJ09B0310-0100 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Image 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M + 1 MSB LSB Longword data Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 MSB LSB Figure 2.10 Memory Data Formats Rev. 1.00 Sep. 21, 2006 Page 32 of 658 REJ09B0310-0100 Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM* , STM* 5 5 1 1 Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L Types 5 MOVFPE*3, MOVTPE*3 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* Logic operations Shift Bit manipulation Branch System control 4 19 AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 4 8 14 5 9 1 Total: 65 BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B BIAND, BOR, BIOR, BXOR, BIXOR BCC*2, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP - - - Block data transfer EEPMOV Notes: B: Byte size; W: Word size; L: Longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. BCC is the generic name for conditional branch instructions. 3. Cannot be used in this LSI. 4. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. 5. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot be used as an STM/LDM register. Rev. 1.00 Sep. 21, 2006 Page 33 of 658 REJ09B0310-0100 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 1.00 Sep. 21, 2006 Page 34 of 658 REJ09B0310-0100 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size*1 B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM*2 STM* 2 L L @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot be used as an STM/LDM register. Rev. 1.00 Sep. 21, 2006 Page 35 of 658 REJ09B0310-0100 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8-bit x 8-bit 16-bit or 16-bit x 16-bit 32-bit. Instruction Size* ADD SUB B/W/L ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8bit x 8-bit 16-bit or 16-bit x 16-bit 32-bit. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16-bit / 8-bit 8-bit quotient and 8-bit remainder or 32-bit / 16-bit 16-bit quotient and 16-bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 21, 2006 Page 36 of 658 REJ09B0310-0100 Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Instruction Size* DIVXS B/W CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS*2 B @ERd - 0, 1 ( Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. Rev. 1.00 Sep. 21, 2006 Page 37 of 658 REJ09B0310-0100 Section 2 CPU Table 2.5 Logic Operations Instructions Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Instruction Size* AND B/W/L OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L Rd Rd Takes the one's complement (logical complement) of data in a general register. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Sep. 21, 2006 Page 38 of 658 REJ09B0310-0100 Section 2 CPU Table 2.6 Shift Instructions Function Rd (shift) Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L B/W/L Rd (rotate) Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. Rd (rotate) Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Size refers to the operand size. B: Byte W: Word L: Longword Instruction Size* SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * B/W/L Rev. 1.00 Sep. 21, 2006 Page 39 of 658 REJ09B0310-0100 Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Function 1 ( Instruction Size* BSET B BCLR B 0 ( BNOT B ( BTST B ( BAND B C ( BIAND B C ( BOR B C ( BIOR B C ( Note: * Size refers to the operand size. B: Byte Rev. 1.00 Sep. 21, 2006 Page 40 of 658 REJ09B0310-0100 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ( BIXOR B C ( BLD B ( BILD B ( BST B C ( BIST B C ( Note: * Size refers to the operand size. B: Byte Rev. 1.00 Sep. 21, 2006 Page 41 of 658 REJ09B0310-0100 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size - Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Condition Always Never CZ=0 CZ=1 C=0 JMP BSR JSR RTS - - - - Branches unconditionally to a specified address. Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev. 1.00 Sep. 21, 2006 Page 42 of 658 REJ09B0310-0100 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* - - - B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper eight bits are valid. STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper eight bits are valid. ANDC ORC XORC NOP Note: * B B B - CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. Size refers to the operand size. B: Byte W: Word Rev. 1.00 Sep. 21, 2006 Page 43 of 658 REJ09B0310-0100 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size - Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next: if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W - Rev. 1.00 Sep. 21, 2006 Page 44 of 658 REJ09B0310-0100 Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register field Specifies a general register. Address registers are specified by 3-bit, and data registers by 3-bit or 4-bit. Some instructions have two register fields, and some have no register field. * Effective address extension 8-, 16-, or 32-bit specifying immediate data, an absolute address, or a displacement. * Condition field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS (2) Operation field and register fields op rn rm ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) Rev. 1.00 Sep. 21, 2006 Page 45 of 658 REJ09B0310-0100 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode 1 2 3 4 5 6 7 8 Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper eight bits are all assumed to be 0 (H'00). Rev. 1.00 Sep. 21, 2006 Page 46 of 658 REJ09B0310-0100 Section 2 CPU 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register Indirect with Post-Increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Register Indirect with Pre-Decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper eight bits are all assumed to be 0 (H'00). Rev. 1.00 Sep. 21, 2006 Page 47 of 658 REJ09B0310-0100 Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24-bit and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24-bit of this branch address are valid; the upper eight bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128-byte (-63 to +64 words) or -32766 to +32768-byte (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Rev. 1.00 Sep. 21, 2006 Page 48 of 658 REJ09B0310-0100 Section 2 CPU 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, see section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode Rev. 1.00 Sep. 21, 2006 Page 49 of 658 REJ09B0310-0100 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper eight bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect (@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 * Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 1.00 Sep. 21, 2006 Page 50 of 658 REJ09B0310-0100 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Rev. 1.00 Sep. 21, 2006 Page 51 of 658 REJ09B0310-0100 Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. * Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, see section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state In a product which has a bus master other than the CPU, the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. For details, see section 6, Bus Controller (BSC). * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 52 of 658 REJ09B0310-0100 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details, refer to section 22, Power-Down Modes. Figure 2.13 State Transitions Rev. 1.00 Sep. 21, 2006 Page 53 of 658 REJ09B0310-0100 Section 2 CPU 2.9 2.9.1 Usage Notes Note on TAS Instruction Usage To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, registers ER0, ER1, ER4, and ER5 should be used. 2.9.2 Note on STM/LDM Instruction Usage Since the ER7 register is used as the stack pointer in an STM/LDM instruction, it cannot be used as a register that allows save (STM) or restore (LDM) operation. Two to four registers can be saved/restored by single STM/LDM instruction. Available registers are listed below. Two: ER0 and ER1, ER2 and ER3, ER4 and ER5 Three: ER0 to ER2, ER4 to ER6 Four: ER0 to ER3 The STM/LDM instruction with ER7 is not created by the Renesas Technology H8S or H8/300 series C/C++ compilers. 2.9.3 Note on Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the data of the target bit, and write data in byte units. Special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port. In addition, the BCLR instruction can be used to clear the flag of the internal I/O register. In this case, if the flag to be cleared has been set to 1 by an interrupt processing routine, the flag need not be read before executing the BCLR instruction. Rev. 1.00 Sep. 21, 2006 Page 54 of 658 REJ09B0310-0100 Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4*, which starts from the address indicated by ER5, to the address indicated by ER6. ER5 ER6 ER5 + R4 ER6 + R4 2. Set R4 and ER6 so that the end address of the destination address (value of ER6 + R4) does not exceed H'00FFFFFF (the value of ER6 must not change from H'00FFFFFF to H'01000000 during execution). ER5 ER6 ER5 + R4 Invalid H'FFFFFFF ER6 + R4 Rev. 1.00 Sep. 21, 2006 Page 55 of 658 REJ09B0310-0100 Section 2 CPU Rev. 1.00 Sep. 21, 2006 Page 56 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports five operating modes (modes 1 to 3, 6, and 7). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 MCU Operating Mode Selection MD0 1 0 CPU Operating Mode Description Advanced Advanced On-chip ROM disabled extended mode Single-chip mode, On-chip ROM enabled extended mode Single-chip mode, On-chip ROM enabled extended mode On-Chip ROM Disabled Enabled MCU Operating Mode MD2* MD1 1 2 0 0 0 1 3 0 1 1 Normal Enabled 6 7 Note: * 1 1 1 1 0 1 Emulation Emulation On-chip emulation mode Enabled On-chip emulation mode Enabled This pin is not supported in SDIP-64 and QFP-64. The input value of MD2 is fixed to 0. Mode 1 operates in on-chip ROM disabled extended mode. On-chip emulation is not supported. Modes 2 and 3 operate in single-chip mode or on-chip ROM enabled extended mode. Modes 0, 4, and 5 are not available in this LSI. Modes 6 and 7 are operating modes for a special purpose. Thus, mode pins should be set to enable mode 2 or 3 in the normal program execution state. Mode pin settings should not be changed during operation. Mode 4 is a boot mode for programming or erasing the flash memory. For details, see section 19, Flash Memory (0.18-m F-ZTAT Version). Modes 6 and 7 are on-chip emulation modes. In these modes, this LSI is controlled by an on-chip emulator (E10A) via the H-UDI, thus enabling on-chip emulation. These modes are not supported in SDIP-64 and QFP-64. Rev. 1.00 Sep. 21, 2006 Page 57 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating modes. For details on the bus control register (BCR), see section 6.3.1, Bus Control Register (BCR). * Mode control register (MDCR) * System control register (SYSCR) * Serial timer control register (STCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit 7 Bit Name EXPE Initial Value 0 R/W R/W Description Extended Mode Enable Mode 1 This bit is fixed to 1 and cannot be modified. Mode 2 and 3 0: Single-chip mode 1: On-chip ROM enabled extended mode 6 to 3 -- 2 1 0 MDS2 MDS1 MDS0 All 0 --* --* --* 1 2 2 R R R R Reserved The initial value should not be changed. Mode Select 2 to 0 These bits indicate the input levels at mode pins (MD2, MD1, and MD0) (the current operating mode). The MDS2, MDS1, and MDS0 bits correspond to the MD2, MD1, and MD0 pins, respectively. These bits are read-only bits and cannot be written to. The input levels of the mode pins (MD2, MD1, and MD0) are latched into these bits when MDCR is read. These latches are canceled by a reset. Notes: 1. The initial value is determined by the MD2 pin. The MD2 pin is not supported in SDIP64 and QFP-64. This bit is always read as 0. 2. The initial value is determined by the MD1 and MD0 pins. Rev. 1.00 Sep. 21, 2006 Page 58 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space. Bit 7 6 Bit Name -- IOSE Initial Value 0 0 R/W R R/W Description Reserved The initial value should not be changed. IOS Enable Controls AS/IOS pin function in extended mode. 0: AS pin Low output when accessing the external area. 1: IOS pin Low output when accessing the specified address from H'(FF)F000 to H'(FF)F7FF 5 4 INTM1 INTM0 0 0 R R/W Interrupt Control Select Mode 1, 0 These bits select the interrupt control mode of the interrupt controller. For details on the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset Indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows 1: A reset is caused by an external reset 2 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input Rev. 1.00 Sep. 21, 2006 Page 59 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes Bit 1 0 Bit Name -- RAME Initial Value 0 1 R/W R/W R/W Description Reserved The initial value should not be changed. RAM Enable Enables or disables on-chip RAM. 0: On-chip RAM is disabled 1: On-chip RAM is enabled 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit 7 6 5 Bit Name -- IICX1 IICX0 Initial Value 0 0 0 R/W R/W R/W R/W Description Reserved The initial value should not be changed. I2C Transfer Rate Select 1, 0 These bits control the IIC operation. These bits select the transfer rate in master mode together with bits CKS2 to 2 CKS0 in the I C bus mode register (ICMR). For details on the transfer rate, see table 16.3. Rev. 1.00 Sep. 21, 2006 Page 60 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes Bit 4 Bit Name IICE Initial Value 0 R/W R/W Description I2C Master Enable Enables or disables CPU access to IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR, and DDCSWR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL), and SCI registers (SMR, BRR, and SCMR). 0: SCI_1 registers are accessed in areas from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. SCI_2 registers are accessed in areas from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. Access is prohibited in areas from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 1: IIC_1 registers are accessed in areas from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed in areas from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. IIC_0 registers are accessed in areas from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. DDCSWR is accessed in areas of H'(FF)FEE6. 3 FLSHE 0 R/W Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), powerdown state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (BCR2, WSCR, PCSR, and SYSCR2). 0: Control registers of power-down state and peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. Area from H'(FF)FEA8 to H'(FF)FEAE is reserved. 1: Control registers of flash memory are accessed in an area from H'(FF)FEA8 to H'(FF)FEAE. Area from H'(FF)FF80 to H'(FF)FF87 is reserved. 2 1 0 -- ICKS1 ICKS0 0 0 0 R/(W) Reserved The initial value should not be changed. R/W R/W Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, see section 13.3.4, Timer Control Register (TCR). Rev. 1.00 Sep. 21, 2006 Page 61 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 4 carries bus control signals. However, as these series have a maximum of 16 address outputs, an external address can be specified correctly only when the I/O strobe function of the AS/IOS pin is used. Mode 1 does not support on-chip emulation. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. However, as these series have a maximum of 16 address outputs, an external address can be specified correctly only when the I/O strobe function of the AS/IOS pin is used. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port 3 functions as a data bus, and part of port 4 carries bus control signals. 3.3.3 Mode 3 The CPU can access a 64-Kbyte address space in normal mode. The on-chip ROM is enabled. After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use external addresses. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They can be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port 3 functions as a data bus, and part of port 4 carries bus control signals. In this operating mode, the amount of on-chip ROM is limited to 56 Kbytes and the amount of onchip RAM is limited to 4 Kbytes. Rev. 1.00 Sep. 21, 2006 Page 62 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 to 4 vary depending on the operating mode. Table 3.2 shows their functions in each operating mode. Table 3.2 Port Port 1 Port 2 Port 3 Port 4 P47 P46 P45 to P43 P42 to P40 [Legend] P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After a reset Pin Functions in Each Mode Mode 1 A A D P*/C C*/P C P Mode 2 P*/A P*/A P*/D P*/C P*/C P*/C P Mode 3 P*/A P*/A P*/D P*/C P*/C P*/C P Rev. 1.00 Sep. 21, 2006 Page 63 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes 3.5 Address Map Figures 3.1 and 3.2 show the address map in each operating mode. Mode 1 On-chip ROM disabled extended mode (Advanced mode) H'000000 Mode 2 (EXPE = 1) On-chip ROM enabled extended mode (Advanced mode) H'000000 H'000000 Mode 2 (EXPE = 0) Single-chip mode (Advanced mode) On-chip ROM 512 Kbytes External address space H'07FFFF H'080000 H'0FFFFF H'100000 H'FEFFFF H'FF0000 H'FEFFFF H'FF0000 H'07FFFF H'080000 H'0FFFFF External address space On-chip ROM 512 Kbytes Reserved area Reserved area Reserved area Reserved area H'FFD07F H'FFD080 On-chip RAM* 8064 bytes H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF External address space Internal I/O register 2 On-chip RAM 128 bytes* H'FFD07F H'FFD080 On-chip RAM* 8064 bytes H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF H'FFD080 On-chip RAM 8064 bytes H'FFEFFF External address space H'FFF800 Internal I/O register 2 On-chip RAM 128 bytes* Internal I/O register 1 Internal I/O register 1 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Internal I/O register 2 On-chip RAM 128 bytes* Internal I/O register 1 Note: * This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Figure 3.1 Address Map (1) Rev. 1.00 Sep. 21, 2006 Page 64 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes Mode 3 (EXPE = 1) On-chip ROM enabled extended mode (Normal mode) Mode 3 (EXPE = 0) Single-chip mode (Normal mode) H'0000 H'0000 On-chip ROM On-chip ROM H'DFFF External address space H'E080 On-chip RAM* H'DFFF H'E080 On-chip RAM H'EFFF External address space H'F800 H'EFFF H'F000 H'F7FF H'F800 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O register 2 On-chip RAM 128 bytes* Internal I/O register 2 On-chip RAM 128 bytes Internal I/O register 1 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O register 1 Note: * This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. Figure 3.2 Address Map (2) Rev. 1.00 Sep. 21, 2006 Page 65 of 658 REJ09B0310-0100 Section 3 MCU Operating Modes Rev. 1.00 Sep. 21, 2006 Page 66 of 658 REJ09B0310-0100 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direct transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in the program execution state. Direct transition Trap instruction Low Rev. 1.00 Sep. 21, 2006 Page 67 of 658 REJ09B0310-0100 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 4.2 lists the correspondence between exception sources and vector addresses. Table 4.2 Exception Handling Vector Table Vector Number Normal Mode 0 1 | 5 6 7 8 9 10 11 Reserved for system use 12 | 15 16 17 18 19 20 21 22 23 24 | 127 Vector Address Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 | H'0001FC to H'0001FF Exception Source Reset Reserved for system use H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 | H'00FE to H'00FF Direct transition External interrupt (NMI) Trap instruction (four sources) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Rev. 1.00 Sep. 21, 2006 Page 68 of 658 REJ09B0310-0100 Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and then program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence. Rev. 1.00 Sep. 21, 2006 Page 69 of 658 REJ09B0310-0100 Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction RES Internal address bus (1) U (1) L (3) Internal read signal Internal write signal High Internal data bus (2) U (2) L (4) (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction Figure 4.1 Reset Sequence (Mode 2) 4.3.2 Interrupts Immediately after Reset If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after a reset, make sure that this instruction initializes the SP (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled After a reset is cancelled, the module stop control registers (MSTPCRH, MSTPCRL, MSTPCRA, and MSTPCRB) are initialized, and all modules except the DTC operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode. For details on module stop mode, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 70 of 658 REJ09B0310-0100 Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved in the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. 4.5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved in the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling. Table 4.3 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 I Set to 1 Set to 1 UI Retains value prior to execution Set to 1 Rev. 1.00 Sep. 21, 2006 Page 71 of 658 REJ09B0310-0100 Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode Advanced mode SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 1.00 Sep. 21, 2006 Page 72 of 658 REJ09B0310-0100 Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what occurs when the SP value is odd. CCR SP PC SP SP R1L H'FFEFFA H'FFEFFB H'FFEFFC PC H'FFEFFD H'FFEFFF TRAPA instruction executed SP set to H'FFEFFF [Legend] CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer MOV.B R1L, @-ER7 Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which interrupt control mode is 0 in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 1.00 Sep. 21, 2006 Page 73 of 658 REJ09B0310-0100 Section 4 Exception Handling Rev. 1.00 Sep. 21, 2006 Page 74 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks. * Three-level interrupt mask control By means of the interrupt control mode, I and UI bits in CCR and ICR, 3-level interrupt mask control is performed. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be independently selected for IRQ7 to IRQ0. * DTC control The DTC can be activated by an interrupt request. * General ports for IRQ7 to IRQ0 input are selectable Rev. 1.00 Sep. 21, 2006 Page 75 of 658 REJ09B0310-0100 Section 5 Interrupt Controller INTM1, INTM0 SYSCR NMIEG NMI input NMI input Interrupt request Vector number IRQ input IRQ input ISR ISCR IER I, UI Priority level determination CPU CCR Internal interrupt sources SWDTEND to IICI1 ICR Interrupt controller [Legend] ICR: ISCR: IER: ISR: SYSCR: Interrupt control register IRQ sense control register IRQ enable register IRQ status register System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 1.00 Sep. 21, 2006 Page 76 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Symbol NMI IRQ7 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable external interrupt pin Rising edge or falling edge can be selected Maskable external interrupt pins Rising-edge, falling-edge, or both-edge detection, or levelsensing can be selected individually for each pin. 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). * * * * * * Interrupt control registers A to D (ICRA to ICRD) Address break control register (ABRKCR) Break address registers A to C (BARA to BARC) IRQ sense control registers (ISCRH, ISCRL) IRQ enable registers (IER) IRQ status registers (ISR) Rev. 1.00 Sep. 21, 2006 Page 77 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in table 5.2. Bit 7 to 0 Bit Name ICRn7 to ICRn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) Note: n: A to D Table 5.2 Correspondence between Interrupt Source and ICR Register Bit 7 6 5 4 3 2 1 0 Note: Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 DTC WDT_0 WDT_1 ICRB A/D converter FRT -- -- TMR_0 TMR_1 TMR_X, TMR_Y -- ICRC SCI_0 SCI_1 -- IIC_0 IIC_1 -- -- -- ICRD TCM_0 TCM_1 -- -- -- -- -- -- n: A to D : Reserved. The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 78 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested. Bit 7 Bit Name CMF Initial Value Undefined R/W R Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Clearing condition] When an exception handling is executed for an address break interrupt. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE bit is set to 1. 6 to 1 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. 0 BIE 0 R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled Rev. 1.00 Sep. 21, 2006 Page 79 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. * BARA Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus. * BARB Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus. * BARC Bit 7 to 1 Bit Name A7 to A1 Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 21, 2006 Page 80 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. * ISCRH Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 7 to 4) * ISCRL Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 3 to 0) Rev. 1.00 Sep. 21, 2006 Page 81 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER) IER enables and disables interrupt requests IRQ7 to IRQ0. * IER Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable The IRQn interrupt request is enabled when this bit is 1. (n = 7 to 0) 5.3.6 IRQ Status Registers (ISR) ISR is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests. * ISR Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W Description R/(W)* [Setting condition] R/(W)* When the interrupt source selected by the ISCR R/(W)* registers occurs R/(W)* [Clearing conditions] R/(W)* * When writing 0 to IRQnF flag after reading IRQnF = 1 R/(W)* * When interrupt exception handling is executed R/(W)* when low-level detection is set and IRQn input is R/(W)* high * When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 7 to 0) Note: * Only 0 can be written for clearing the flag. Rev. 1.00 Sep. 21, 2006 Page 82 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupt Sources The interrupt sources of external interrupts are NMI and IRQ7 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. (1) NMI Interrupt The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or falling edge on the NMI pin. (2) IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. When the interrupts are requested while IRQ7 to IRQ0 interrupt requests are generated at low level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling starts. Then put the relevant IRQ input back to high level within the interrupt handling routine and clear the IRQnF bit (n = 7 to 0) in ISR to 0. If the relevant IRQ input is put back to high level before the interrupt handling starts, the relevant interrupt may not be executed. The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function. A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2. Rev. 1.00 Sep. 21, 2006 Page 83 of 658 REJ09B0310-0100 Section 5 Interrupt Controller IRQnSCA, IRQnSCB IRQnF IRQn Edge/level detection circuit S R IRQnE Q IRQn interrupt request n = 7 to 0 Clear signal Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 5.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. 2. The control level for each interrupt can be set by ICR. 3. The DTC can be activated by an interrupt request from an on-chip peripheral module. 4. An interrupt request that activates the DTC is not affected by the interrupt control mode or the status of the CPU interrupt mask bits. Rev. 1.00 Sep. 21, 2006 Page 84 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Tables Tables 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to interrupt control level 1 (priority) by the interrupt control level and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to interrupt control level 0 (no priority). Table 5.3 Origin of Interrupt Source External pin Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Vector Number 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 47 48 49 50 51 52 53 54 55 Normal Mode H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 -- ICRB7 -- Priority High DTC WDT_0 WDT_1 -- SWDTEND (Software activation data transfer end) WOVI0 (Interval timer) WOVI1 (Interval timer) Address break A/D converter ADI (A/D conversion end) -- Reserved for system use FRT ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use ICRB6 Low Rev. 1.00 Sep. 21, 2006 Page 85 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Origin of Interrupt Source TCM_0 Vector Address Name TICI0 (Input capture) TCMI0 (Compare match) TOVMI0 (MAX cycle overflow) TOVI0 (Overflow) TICI1 (Input capture) TCMI1 (Compare match) TOVMI1 (MAX overflow) TOVI1 (Overflow) CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) Reserved for system use CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) Reserved for system use ERI0 (Reception error 0) RXI0 (Reception completion 0) TXI0 (Transmission data empty 0) TEI0 (Transmission end 0) ERI1 (Reception error 1) ERI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) Reserved for system use Vector Number 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 91 Normal Mode H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 H'00FE Advanced Mode H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 H'0001FC Low ICRC3 ICR ICRD7 Priority High TCM_1 ICRD6 TMR_0 ICRB3 TMR_1 ICRB2 TMR_X TMR_Y ICRB1 -- SCI_0 -- ICRC7 SCI_1 ICRC6 IIC_0 92 IICI0 (1-byte transmission/reception completion) 93 Reserved for system use 94 IICI1 (1-byte transmission/reception completion) 95 Reserved for system use Reserved for system use 96 127 ICRC4 IIC_1 Rev. 1.00 Sep. 21, 2006 Page 86 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.4 Interrupt Control Modes Priority Setting Registers ICR Interrupt Mask Bits I Interrupt SYSCR Control Mode INTM1 INTM0 0 0 0 Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR. 1 0 1 ICR I, UI Rev. 1.00 Sep. 21, 2006 Page 87 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Figure 5.3 shows a block diagram of the priority determination circuit. I ICR UI Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.3 Block Diagram of Interrupt Control Operation Rev. 1.00 Sep. 21, 2006 Page 88 of 658 REJ09B0310-0100 Section 5 Interrupt Controller (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the interrupts selected in each interrupt control mode. Table 5.5 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bits Interrupt Control Mode I 0 0 1 1 0 1 UI * * * 0 1 [Legend] *: Don't care Selected Interrupts All interrupts (interrupt control level 1 has priority) NMI and address break interrupts All interrupts (interrupt control level 1 has priority) NMI, address break, and interrupt control level 1 interrupts NMI and address break interrupts (2) Default Priority Determination The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.6 shows operations and control signal functions in each interrupt control mode. Rev. 1.00 Sep. 21, 2006 Page 89 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control 3-Level Control I IM IM UI -- IM ICR PR PR Interrupt Control Mode INTM1 0 1 0 Setting INTM0 0 1 Default Priority Determination [Legend] : Interrupt operation control is performed IM: Used as an interrupt mask bit PR: Priority is set --: Not used 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than NMI and address break are masked by ICR and the I bit of CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, the interrupt controller holds pending interrupt requests other than NMI and address break. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Sep. 21, 2006 Page 90 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Program execution state Interrupt generated? Yes Yes No NMI No An interrupt with interrupt control level 1? No Hold pending Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 IICI1 Yes Yes IICI1 Yes No No I=0 Yes No Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Sep. 21, 2006 Page 91 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. * An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. * An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both the I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown below. Figure 5.5 shows a state transition diagram. * All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...) * Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI = 0. * Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1. I All interrupt requests are accepted I 0 0 1, UI Only NMI, address break, and interrupt control level 1 interrupt requests are accepted I Exception handling execution or I 1, UI 1 0 UI 0 Exception handling execution or UI 1 Only NMI and address break interrupt requests are accepted Figure 5.5 State Transition in Interrupt Control Mode 1 Rev. 1.00 Sep. 21, 2006 Page 92 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When both the I and UI bits are set to 1, only NMI and address break interrupt requests are accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit does not affect acceptance of interrupt requests. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Sep. 21, 2006 Page 93 of 658 REJ09B0310-0100 Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI No An interrupt with interrupt control level 1? No Hold pending Yes No No IRQ1 Yes IICI1 Yes No IRQ0 Yes IRQ1 Yes IICI1 Yes No IRQ0 Yes I=0 Yes No I=0 No Yes No UI = 0 Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 1.00 Sep. 21, 2006 Page 94 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 1.00 Sep. 21, 2006 Page 95 of 658 REJ09B0310-0100 REJ09B0310-0100 Interrupt is accepted Instruction prefetch Stack access Vector fetch Internal processing Prefetch of instruction in Internal processing interrupt handling routine (1) (3) (5) (7) (9) (11) (13) (2) (4) (6) (8) (10) (12) (14) (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and CCR Vector address Start address of interrupt handling routine (contents of vector address) Start address of interrupt handling routine ((13) = (10) (12)) First instruction in interrupt handling routine Section 5 Interrupt Controller Interrupt level determination and wait for end of instruction Rev. 1.00 Sep. 21, 2006 Page 96 of 658 Interrupt request signal Internal address bus Internal read signal Internal write signal Figure 5.7 Interrupt Exception Handling Internal data bus (1) (2) (4) (3) (5) (7) Instruction prefetch address (Not executed. Address is saved as PC contents, becoming return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP - 2 SP - 4 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.7 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.7 No. 1 2 3 4 5 6 Interrupt Response Times Normal Mode 1 Execution Status Interrupt priority determination* Advanced Mode 3 1 to (19 + 2*SI) 2*SK 2*SI 2*SI 2 12 to 32 3 Number of wait states until instruction execution 1 to (19 + 2*SI) ends*2 Saving of PC and CCR in stack Vector fetch Instruction fetch* 3 2*SK SI 2*SI 2 11 to 31 Internal processing*4 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.8 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus Symbol Instruction fetch SI Brach address read SJ Stack manipulation SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m [Legend] m: Number of wait states in external device access Rev. 1.00 Sep. 21, 2006 Page 97 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: 1. Interrupt request to CPU 2. Activation request to DTC 3. Both of the above For details on interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.8 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip peripheral module DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, UI Interrupt controller Figure 5.8 Interrupt Control for DTC Rev. 1.00 Sep. 21, 2006 Page 98 of 658 REJ09B0310-0100 Section 5 Interrupt Controller The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source It is possible to select a DTC activation request or CPU interrupt request for an interrupt source with the DTCE bit in DTCERA to DTCERE of the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit in MRB of the DTC. When the DTC performs the specified number of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU. (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.4, Location of Register Information and DTC Vector Table, for the respective priorities. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit in DTCERA to DTCERE of the DTC and the DISEL bit in MRB of the DTC. Table 5.9 Interrupt Source Selection and Clearing Control Settings DTC DTCE 0 1 DISEL * 0 1 x Interrupt Source Selection/Clearing Control DTC CPU x [Legend] : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. x: The relevant interrupt cannot be used. *: Don't care Rev. 1.00 Sep. 21, 2006 Page 99 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.7 5.7.1 Address Breaks Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.7.2 Block Diagram Figure 5.9 shows a block diagram of the address break function. BAR ABRKCR Match signal Comparator Control logic Address break interrupt request Internal address Prefetch signal (internal signal) Figure 5.9 Block Diagram of Address Break Function Rev. 1.00 Sep. 21, 2006 Page 100 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.7.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction. With an address break interrupt, interrupt mask control by the I and UI bits in the CPU's CCR is ineffective. The register settings when the address break function is used are as follows. 1. Set the break address in bits A23 to A1 in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be requested if the BIE bit is cleared to 0. When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is requested. If necessary, the source should be identified in the interrupt handling routine. 5.7.4 Usage Notes 1. With the address break function, the address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. 2. In normal mode, no comparison is made with address lines A23 to A16. 3. If a branch instruction (Bcc, BSR) jump instruction (JMP, JSR), RTS instruction, or RTE instruction is located immediately before the address set in BAR, execution of this instruction will output a prefetch signal for that address, and an address break may be requested. This can be prevented by not making a break address setting for an address immediately following one of these instructions, or by determining within the interrupt handling routine whether interrupt handling was initiated by a genuine condition occurrence. 4. As an address break interrupt is generated by a combination of the internal prefetch signal and address, the timing of the start of interrupt exception handling depends on the content and execution cycle of the instruction at the set address and the preceding instruction. Figure 5.10 shows some address timing examples. Rev. 1.00 Sep. 21, 2006 Page 101 of 658 REJ09B0310-0100 Section 5 Interrupt Controller * Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Stack save Vector fetch Internal Instruction operation fetch Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP NOP NOP execution execution execution Interrupt exeption handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction is executed at breakpoint address H'0312 and next address, H'0314; fetch from address H'0316 starts after end of exception handling. * Program area in on-chip memory, 2-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch operation fetch Stack save Vector fetch Internal Instruction operation fetch Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP execution MOV.W execution Interrupt exeption handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP MOV.W #xx : 16,Rd NOP NOP Breakpoint MOV instruction is executed at breakpoint address H'0312, NOP instruction at next address, H'0316, is not executed; fetch from address H'0316 starts after end of exception handling. * Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address (Not available in this LSI) Instruction fetch Instruction fetch Instruction fetch Internal operation Stack save Vector fetch Internal operation Address bus H'0310 H'0312 H'0314 SP-2 SP-4 H'0036 NOP execution Interrupt exeption handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction at breakpoint address H'0312 is not executed; fetch from address H'0312 starts after end of exception handling. Figure 5.10 Examples of Address Break Timing Rev. 1.00 Sep. 21, 2006 Page 102 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.11 shows an example where the CMIEA bit in TCR of the TMR is cleared to 0. The above conflict will not occur if an interrupt enable bit or interrupt source flag is cleared to 0 while the interrupt is disabled. TCR write cycle by CPU CMIA exception handling Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.11 Conflict between Interrupt Generation and Disabling Rev. 1.00 Sep. 21, 2006 Page 103 of 658 REJ09B0310-0100 Section 5 Interrupt Controller 5.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request including NMI issued during data transfer is not accepted until data transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during data transfer, interrupt exception handling starts at a break in the transfer cycles. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.8.4 External Interrupt Pin in Software Standby Mode and Watch Mode * When the pins (IRQ7 to IRQ0) are used as external input pins in software standby mode or watch mode, the pins should not be left floating. * When the external interrupt pins (IRQ3 to IRQ0) are used in software standby and watch modes, the noise canceller should be disabled. 5.8.5 Noise Canceller Switching The noise canceller should be switched when the external input pins (IRQ3 to IRQ0) are high. 5.8.6 IRQ Status Register (ISR) Since IRQnF may be set to 1 according to the pin state after reset, the ISR should be read after reset, and then write 0 in IRQnF (n = 7 to 0). Rev. 1.00 Sep. 21, 2006 Page 104 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters - CPU, and data transfer controller (DTC). 6.1 Features * Basic bus interface 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface A burst ROM interface can be set for basic expansion areas 1-state access or 2-state access can be selected for burst access * Idle cycle insertion An idle cycle can be inserted for external write cycles immediately after external read cycles * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC BSCS20AA_000020020700 Rev. 1.00 Sep. 21, 2006 Page 105 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) External bus control signals Bus controller Internal control signals Bus mode signal BCR WAIT Wait controller CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller 6.2 Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Symbol AS IOS RD WR WAIT Pin Configuration I/O Output Output Output Output Input Function Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). I/O select signal (when the IOSE bit in SYSCR is set to 1). Strobe signal indicating that the external address space is being read. Strobe signal indicating that the external address space is being written and the data bus is enabled. Wait request signal when accessing the external 3-state access space. Rev. 1.00 Sep. 21, 2006 Page 106 of 658 REJ09B0310-0100 Internal data bus WSCR Section 6 Bus Controller (BSC) 6.3 Register Descriptions The bus controller has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). * Bus control register (BCR) * Wait state control register (WSCR) 6.3.1 Bus Control Register (BCR) BCR is used to specify the access mode for the external address space or the I/O area range when the AS/IOS pin is specified as an I/O strobe pin. Bit 7 6 Bit Name -- ICIS0 Initial Value 1 1 R/W R/W R/W Description Reserved The initial value should not be changed. Idle Cycle Insertion Selects whether or not to insert 1-state of the idle cycle between bus cycles when the external write cycle follows the external read cycle. 0: Idle cycle not inserted when the external write cycle follows the external read cycle 1: 1-state idle cycle inserted when the external write cycle follows the external read cycle 5 BRSTRM 0 R/W Burst ROM Enable Selects the bus interface for the external address space. 0: Basic bus interface 1: Burst ROM interface 4 BRSTS1 1 R/W Burst Cycle Select 1 Selects the number of states in the burst cycle of the burst ROM interface. 0: 1 state 1: 2 states Rev. 1.00 Sep. 21, 2006 Page 107 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Bit 3 Bit Name BRSTS0 Initial Value 0 R/W R/W Description Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface. 0: Max, 4 words 1: Max, 8 words 2 1 0 IOS1 IOS0 0 1 1 R/W R/W R/W Reserved The initial value should not be changed. IOS Select 1, 0 Select the address range where the IOS signal is output. For details, refer to table 6.3. 6.3.2 Wait State Control Register (WSCR) WSCR is used to specify the data bus width for external address space access, the number of access states, the wait mode, and the number of wait states for access to external address spaces. The bus width and the number of access states for internal memory and internal I/O registers are fixed regardless of the WSCR settings. Bit 7 6 5 4 Bit Name -- -- ABW AST Initial Value 1 1 1 1 R/W R/W R/W R/W R/W Description Reserved These bits should not be written by 1. Bus Width Control The initial value should not be changed. Access State Control Selects 2 or 3 access states for access to the external address space. This bit also enables or disables wait-state insertion. 0: 2-state access space. Wait state insertion disabled in external address space access 1: 3-state access space. Wait state insertion enabled in external address space access Rev. 1.00 Sep. 21, 2006 Page 108 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Bit 3 2 Bit Name WMS1 WMS0 Initial Value 0 0 R/W R/W R/W Description Wait Mode Select 1, 0 Select the wait mode for access to the external address space when the AST bit is set to 1. 00: Program wait mode 01: Wait disabled mode 10: Pin wait mode 11: Pin auto-wait mode 1 0 WC1 WC0 1 1 R/W R/W Wait Count 1, 0 Select the number of program wait states to be inserted when the external address space is accessed while the AST bit is set to 1. 00: Program wait state is not inserted 01: 1 program wait state is inserted 10: 2 program wait states are inserted 11: 3 program wait states are inserted Rev. 1.00 Sep. 21, 2006 Page 109 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.4 6.4.1 Bus Control Bus Specifications The external address space bus specifications consist of three elements: Bus width, the number of access states, and the wait mode and the number of program wait states. The bus width and the number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller settings. (1) Bus Width A bus width of 8 or 16 bits can be selected via the ABW bit in WSCR. However, 16-bit access space cannot be selected in this LSI. (2) Number of Access States Two or three access states can be selected via the AST bit in WSCR. When the 2-state access space is designated, wait-state insertion is disabled. In the burst ROM interface, the number of access states is determined regardless of the AST bit setting. (3) Wait Mode and Number of Program Wait States When a 3-state access space is designated by the AST bit in WSCR, the wait mode and the number of program wait states to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait states can be selected. Rev. 1.00 Sep. 21, 2006 Page 110 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Table 6.2 shows the bus specifications for the basic bus interface of each area. Table 6.2 Bus Specifications for Basic Bus Interface Bus Specifications Number of Access States Number of Program Wait States ABW 0 1 AST -- 0 1 WMS1 -- -- 0 --* WMS0 -- -- 1 --* WC1 -- -- -- 0 WC0 -- -- -- 0 1 Bus Width Setting prohibited in this LSI 8 8 2 3 3 0 0 0 1 2 3 1 Note: * 0 1 Other than WMS1 = 0 and WMS0 = 1 6.4.2 Advanced Mode The external address space is initialized as the basic bus interface and a 3-state access space. In on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The onchip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1. The onchip RAM and its reserved area are disabled and corresponding addresses are the external address space when the RAME bit is cleared to 0. 6.4.3 Normal Mode The external address space is initialized as the basic bus interface and a 3-state access space. In on-chip ROM disable extended mode, the address space other than on-chip RAM and internal I/O registers is specified as the external address space. In on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM area is enabled when the RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 111 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.4.4 I/O Select Signals The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 Address bus External addresses selected by IOS IOS Figure 6.2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE bit to 1. For details, refer to section 8, I/O Ports. The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR, as shown in table 6.3. Table 6.3 IOS1 0 Address Range for IOS Signal Output IOS0 0 1 IOS Signal Output Range H'(FF)F000 to H'(FF)F03F H'(FF)F000 to H'(FF)F0FF H'(FF)F000 to H'(FF)F3FF H'(FF)F000 to H'(FF)F7FF (Initial value) 1 0 1 Rev. 1.00 Sep. 21, 2006 Page 112 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications when using the basic bus interface, see table 6.2. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used when the external address space is accessed, according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. This LSI has only the upper data bus and only data alignment for the 8-bit access space is applied. The pins for the upper data bus in this LSI are D7 to D0. (1) 8-Bit Access Space Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Word size Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev. 1.00 Sep. 21, 2006 Page 113 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) (2) 16-Bit Access Space (Not available in this LSI) Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size * Even address * Odd address Word size Longword size 1st bus cycle 2nd bus cycle Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) Rev. 1.00 Sep. 21, 2006 Page 114 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.5.2 Valid Strobes Table 6.4 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. This LSI has only the upper data bus and only the RD and HWR signals are enabled. The pin for HWR signal in this LSI is WR. Table 6.4 Area 8-bit access space 16-bit access space (not available in this LSI) Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Byte Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR* RD 2 Upper Data Bus Lower Data Bus (D15 to D8)*1 (D7 to D0)*3 Valid Ports or others Ports or others Valid Invalid Valid Undefined Valid Valid Invalid Valid Undefined Valid Valid Valid Notes: Undefined: Undefined data is output. Invalid: Input state with the input value ignored. Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the data bus. 1. The pins in this LSI are D7 to D0. 2. The pin in this LSI is WR. 3. No pins are available in this LSI. Rev. 1.00 Sep. 21, 2006 Page 115 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.5.3 (1) Basic Operation Timing 8-Bit, 2-State Access Space Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. This LSI does not have the lower data bus (D7 to D0) and LWR pin. The pins for the upper data bus (D15 to D8) in this LSI are D7 to D0 and the pin for the HWR signal is WR. Bus cycle T1 T2 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space Rev. 1.00 Sep. 21, 2006 Page 116 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Access Space Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. This LSI does not have the lower data bus (D7 to D0) and LWR pin. The pins for the upper data bus (D15 to D8) in this LSI are D7 to D0 and the pin for the HWR signal is WR. Bus cycle T1 T2 T3 Address bus AS/IOS (IOSE = 1) AS/IOS (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Invalid HWR Write D15 to D8 Valid Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space Rev. 1.00 Sep. 21, 2006 Page 117 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (TW). There are three ways of inserting wait states: Program wait insertion, pin wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin. (1) Program Wait Mode A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits in WSCR. (2) Pin Wait Mode A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states to be inserted for each external device. (3) Pin Auto-Wait Mode A specified number of wait states TW can be inserted automatically between the T2 state and T3 state when accessing the external address space according to the settings of the WC1 and WC0 bits if the WAIT pin is low at the falling edge of in the last T2 state. Even if the WAIT pin is held low, TW states can be inserted only up to the specified number of states. This function enables the low-speed memory interface only by inputting the chip select signal to the WAIT pin. Figure 6.7 shows an example of wait state insertion timing in pin wait mode. The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input disabled. Rev. 1.00 Sep. 21, 2006 Page 118 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) By program wait T1 T2 TW By WAIT pin TW TW T3 WAIT Address bus AS/IOS (IOSE = 0) RD Read Data bus Read data WR Write Data bus Write data Note: shown in clock indicates the WAIT pin sampling timing. Figure 6.7 Example of Wait State Insertion Timing (Pin Wait Mode) Rev. 1.00 Sep. 21, 2006 Page 119 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.6 Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by setting the BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected for burst ROM access. 6.6.1 Basic Operation Timing The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1 or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR. Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight words is performed when the BRSTS0 bit in BCR is set to 1. The basic access timing for the burst ROM space is shown in figures 6.8 and 6.9. Full access Burst access T1 T2 T3 T1 T2 T1 T2 Address bus Only lower address changes AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.8 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) Rev. 1.00 Sep. 21, 2006 Page 120 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Full access Burst access T1 T1 T1 T2 Address bus Only lower address changes AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.9 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. 6.7 Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces. If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.10 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.10 (a), with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In figure 6.10 (b), an idle cycle is inserted, thus preventing data collision. Rev. 1.00 Sep. 21, 2006 Page 121 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Bus cycle A Bus cycle B Bus cycle A Bus cycle B TI T1 T2 T1 T2 T3 T1 T2 T1 T2 T3 Address bus RD WR Address bus RD WR Data bus Data bus Data collision Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion Figure 6.10 Examples of Idle Cycle Operation Table 6.5 shows the pin states in an idle cycle. Table 6.5 Pins A15 to A0, IOS D7 to D0 AS RD WR Pin States in Idle Cycle Pin State Contents of immediately following bus cycle High impedance High High High Rev. 1.00 Sep. 21, 2006 Page 122 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) 6.8 Bus Arbitration The bus controller has a bus arbiter that arbitrates bus master operations. There are two bus masters - the CPU and DTC - that perform read/write operations when they have possession of the bus. 6.8.1 Priority of Bus Masters Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal to the bus master making the request at the designated timing. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) 6.8.2 Bus Transfer Timing When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. Each bus master can relinquish the bus at the timings given below. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the DTC. * DTC bus transfer timing The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. For details, refer to the H8S/2600 Series, H8S/2000 Series Software Manual. If the CPU is in sleep mode, the bus is transferred immediately. (2) DTC The DTC has the highest bus master priority. The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC does not release the bus until it completes its operation. Rev. 1.00 Sep. 21, 2006 Page 123 of 658 REJ09B0310-0100 Section 6 Bus Controller (BSC) Rev. 1.00 Sep. 21, 2006 Page 124 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'(FF)EC00 to H'(FF)EFFF in on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. DTCH80CA_000020020300 Rev. 1.00 Sep. 21, 2006 Page 125 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.1 Features * Transfer is possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes are available * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 16 Mbytes address space is possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request DTC activation request [Legend] MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERE: DTVECR: DTC mode register A, B DTC transfer count register A, B DTC source address register DTC destination address register DTC enable registers A to E DTC vector register Figure 7.1 Block Diagram of DTC Rev. 1.00 Sep. 21, 2006 Page 126 of 658 REJ09B0310-0100 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERE DTVECR Section 7 Data Transfer Controller (DTC) 7.2 Register Descriptions The DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to on-chip RAM. * DTC enable register (DTCER) * DTC vector register (DTVECR) Rev. 1.00 Sep. 21, 2006 Page 127 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W -- -- Description Source Address Mode 1, 0 These bits specify an SAR operation after a data transfer. 0*: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined -- -- Destination Address Mode 1, 0 These bits specify a DAR operation after a data transfer. 0*: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined -- -- DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined -- DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined -- DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer [Legend] *: Don't care Rev. 1.00 Sep. 21, 2006 Page 128 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit 7 Bit Name Initial Value CHNE Undefined R/W -- Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, see section 7.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. 6 DISEL Undefined -- DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time data transfer ends. (DTC does not clear the interrupt source flag which is as an activation source, to 0.) When this bit is cleared to 0, a CPU interrupt request is generated only when the specified number of data transfers ends. (DTC does not clear the interrupt source flag which is as an activation source, to 0.) 5 to 0 -- All undefined -- Reserved These bits have no effect on DTC operation. The write value should always be 0. Rev. 1.00 Sep. 21, 2006 Page 129 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 7.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev. 1.00 Sep. 21, 2006 Page 130 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers (DTCER) DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 and 7.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. Bit 7 6 5 4 3 2 1 0 Bit Name DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When data transfer has ended with the DISEL bit in MRB set to 1 When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed Note: n: A to E Table 7.1 Correspondence between Interrupt Sources and DTCER Register Bit Bit Name 7 6 5 4 3 2 1 0 DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0 DTCERA (16)IRQ0 (17)IRQ1 (18)IRQ2 (28)ADI (48)ICIA (49)ICIB (52)OCIA DTCERB (53)OCIB (56)TICI0 (57)TCMI0 (60)TICI1 (61)TCMI1 (64)CMIA0 (65)CMIB0 (68)CMIA1 DTCERC (69)CMIB1 (72)CMIAY (73)CMIBY (81)RXI0 (82)TXI0 (85)RXI1 DTCERD (86)TXI1 (92)IICI0 (94)IICI1 DTCERE Note: n: A to E ( ): Vector number Rev. 1.00 Sep. 21, 2006 Page 131 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit 7 Bit Name Initial Value SWDTE 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can always be written to this bit. Writing 0 is enabled only after 1 has been read. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is set to 1 and data transfer has ended The specified number of transfers have ended On data transfer by software activation [Holding conditions] * * * 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the SWDTE bit is 0, these bits can be written to. Rev. 1.00 Sep. 21, 2006 Page 132 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.3 Activation Sources The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI1, for example, is the RDRF flag in SCI_1. When an interrupt has been designated as a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block diagram of DTC activation source control. For details on the interrupt controller, see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip peripheral module DTC DTVECR Interrupt controller Interrupt mask CPU Figure 7.2 Block Diagram of DTC Activation Source Control Rev. 1.00 Sep. 21, 2006 Page 133 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 7.3, and the register information start address should be located at the vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the start address of the register information from the vector table set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is a 2-byte unit. Specify the lower two bytes of the register information start address. Lower address B'00 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer B'01 B'10 SAR DAR CRB Register information B'11 4 bytes Figure 7.3 DTC Register Information Location in Address Space Rev. 1.00 Sep. 21, 2006 Page 134 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 Vector Number DTVECR 16 17 18 28 48 49 52 53 56 57 60 61 64 65 68 69 72 73 81 82 85 86 92 94 DTC Vector Address DTCE* Priority High Activation Source Origin Software External pins H'0400 + (vector -- number x 2) H'0420 H'0422 H'0424 H'0438 H'0460 H'0462 H'0468 H'046A H'0470 H'0472 H'0478 H'047A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'04A2 H'04A4 H'04AA H'04AC H'04B8 H'04BC DTCEA7 DTCEA6 DTCEA5 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC2 DTCED1 DTCED0 DTCED7 DTCED4 DTCED3 ADC FRT ADI ICIA ICIB OCIA OCIB TCM_0 TICI0 TCMI0 TCM_1 TICI1 TCMI1 TMR_0 CMIA0 CMIB0 TMR_1 CMIA1 CMIB1 TMR_Y CMIAY CMIBY SCI_0 RXI0 TXI0 SCI_1 RXI1 TXI1 IIC_0 IIC_1 Note: * IICI0 IICI1 Low DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. Rev. 1.00 Sep. 21, 2006 Page 135 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1 No Yes Transfer counter = 0 or DISEL = 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 7.4 DTC Operation Flowchart Rev. 1.00 Sep. 21, 2006 Page 136 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt can be requested. Table 7.3 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Functions in Normal Mode Abbreviation SAR DAR CRA CRB Function Transfer source address Transfer destination address Transfer counter Not used SAR Transfer DAR Figure 7.5 Memory Mapping in Normal Mode Rev. 1.00 Sep. 21, 2006 Page 137 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.4 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has been completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0. Table 7.4 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Functions in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds number of transfers Transfer Count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 7.6 Memory Mapping in Repeat Mode Rev. 1.00 Sep. 21, 2006 Page 138 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.5 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored. The other address register is then incremented, decremented, or left fixed according to the register information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt is requested. Table 7.5 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Functions in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds block size Block size counter Transfer counter 1st block SAR or DAR * * * Block area Transfer DAR or SAR N th block Figure 7.7 Memory Mapping in Block Transfer Mode Rev. 1.00 Sep. 21, 2006 Page 139 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the register information start address stored at the DTC vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source DTC vector address Register information start address Register information CHNE = 1 Register information CHNE = 0 Destination Source Destination Figure 7.8 Chain Transfer Operation Rev. 1.00 Sep. 21, 2006 Page 140 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.5.6 Operation Timing DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Rev. 1.00 Sep. 21, 2006 Page 141 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) DTC activation request DTC request Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 7.11 DTC Operation Timing (Example of Chain Transfer) Rev. 1.00 Sep. 21, 2006 Page 142 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.5.7 Number of DTC Execution States Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number of states required for each execution status. Table 7.6 DTC Execution Status Register Information Vector Read Read/Write I J 1 1 1 6 6 6 Internal Operations M 3 3 3 Mode Normal Repeat Block transfer Data Read K 1 1 N Data Write L 1 1 N [Legend] N: Block size (initial setting of CRAH and CRAL) Table 7.7 Number of States Required for Each Execution Status On-Chip RAM OnOn-Chip RAM (On-chip RAM area (H'(FF)EC00 to other than H'(FF)EC00 Chip On-Chip I/O External ROM Registers H'(FF)EFFF) Device to H'(FF)EFFF) 32 1 -- 1 1 SK Word data read SK Byte data write SL Word data write SL Internal operation SM 1 1 1 1 1 1 1 1 1 1 4 2 4 6 + 2m 1 1 1 2 2 2 3+m 1 1 1 4 2 4 6 + 2m 16 1 -- -- 1 16 1 1 -- 1 8 2 -- -- 2 16 2 -- -- 2 8 2 4 -- 2 8 3 6 + 2m -- 3+m Object to be Accessed Bus width Access states Execution Vector read SI status Register information read/write SJ Byte data read Rev. 1.00 Sep. 21, 2006 Page 143 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of data write is 10 states. 7.6 7.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software 7.6.2 The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 to the SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 1.00 Sep. 21, 2006 Page 144 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.7 7.7.1 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI, RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing. Rev. 1.00 Sep. 21, 2006 Page 145 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.7.2 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform wrap-up processing. Rev. 1.00 Sep. 21, 2006 Page 146 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) 7.8 7.8.1 Usage Notes Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode can not be specified. For details, see section 22, Power-Down Modes. 7.8.2 On-Chip RAM MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR should not be cleared to 0. 7.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm that is set to 1 before making a transition to subactive mode or watch mode. 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter Interrupt sources of the SCI, IIC, or A/D converter are cleared when the DTC reads from or writes to the specified registers, and they cannot be cleared when the DTC reads from or writes to registers or memory that are not specified. Rev. 1.00 Sep. 21, 2006 Page 147 of 658 REJ09B0310-0100 Section 7 Data Transfer Controller (DTC) Rev. 1.00 Sep. 21, 2006 Page 148 of 658 REJ09B0310-0100 Section 8 I/O Ports Section 8 I/O Ports Table 8.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and data registers (DR and ODR) that store output data. DDR, DR, and ODR are not provided for an input-only port. Ports 1 to 3 and P43 to P45 have on-chip input pull-up MOSs. Port 1 to 3 can drive LEDs (with 5mA current sink). P47 and P52 in the H8S/2125 are NMOS push-pull output. Rev. 1.00 Sep. 21, 2006 Page 149 of 658 REJ09B0310-0100 Section 8 I/O Ports Table 8.1 Port Functions Mode 2 Mode 3 (EXPE = 0) P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1/PWX1 P10/PW0/PWX0 P27/PW15/SCK1 P26/PW14/RxD1 P25/PW13/TxD1 P24/PW12/SCL1 P23/PW11/SDA1 P22/PW10 P21/PW9 P20/PW8 P37 P36 P35 P34 P33 P32 P31 P30 On-chip input pull-up MOSs LED drive capability (sink current: 5 mA) On-chip input pull-up MOSs LED drive capability (sink current: 5 mA) I/O Status On-chip input pull-up MOSs LED drive capability (sink current: 5 mA) Port Port 1 Description General I/O port also functioning as address output, PWM output pins, and PWMX output pins Mode 1 A7 A6 A5 A4 A3 A2 A1 A0 (EXPE = 1) A7/P17/PW7 A6/P16/PW6 A5/P15/PW5 A4/P14/PW4 A3/P13/PW3 A2/P12/PW2 A1/P11/PW1/PWX1 A0/P10/PW0/PWX0 A15/P27/PW15/SCK1 A14/P26/PW14/RxD1 A13/P25/PW13/TxD1 A12/P24/PW12/SCL1 A11/P23/PW11/SDA1 A10/P22/PW10 A9/P21/PW9 A8/P20/PW8 Port 2 General I/O port also functioning as address output pin, PWM output pin, SCI_1 I/O pin, and IIC_1 I/O pin A15 A14 A13 A12 A11 A10 A9 A8 Port 3 General I/O port also functioning as data bus I/O pin D7 D6 D5 D4 D3 D2 D1 D0 Rev. 1.00 Sep. 21, 2006 Page 150 of 658 REJ09B0310-0100 Section 8 I/O Ports Mode 2 Port Port 4 Description General I/O port also functioning as extending data bus control I/O, IIC_0 I/O, subclock input, output, interrupt input, and A/D converter external trigger input pins Mode 1 (EXPE = 1) Mode 3 (EXPE = 0) P47/SDA0 P46//EXCL P45 P44 P43 P42/IRQ0 P41/IRQ1 P40/IRQ2/ADTRG I/O Status On-chip input pull-up MOSs (P45 to P43) P47/WAIT/SDA0 P46//EXCL AS/IOS WR RD P42/IRQ0 P41/IRQ1 P40/IRQ2/ADTRG Port 5 General I/O port also functioning as SCI_0 input/output and IIC_0 input/output pins General I/O port also functioning as interrupt input, FRT I/O, TMR_0, TMR_1, TMR_X, and TMR_Y I/O pins P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P67/IRQ3/TMOX/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA/TMIY P61/FTOA/TMOY P60/FTCI/TMCI0/TMIX Port 6 Port 7 General input port also functioning as A/D converter analog input, interrupt input, TCM_0, and TCM_1 input pins P77/AN7/IRQ7/TCMCKI0 P76/AN6/IRQ6/TCMCYI0 P75/AN5/IRQ5/TCMCKI1 P74/AN4/IRQ4/TCMCYI1 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Rev. 1.00 Sep. 21, 2006 Page 151 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus, PWM, and PWMX output pins. Port 1 functions change according to the operating mode. Port 1 has an on-chip input pull-up MOS function that can be controlled by software. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) 8.1.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In mode 1: Each pin of port 1 is address output regardless of the set value of P1DDR. In modes 2 and 3 (EXPE=1): The corresponding port 1 pins are address output or PWM output ports when P1DDR bits are set to 1, and input ports when cleared to 0. In modes 2 and 3 (EXPE=0): The corresponding port 1 pins are output ports or PWM outputs when the P1DDR bits are set to 1, and input ports when cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 152 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read. 8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off status of the port 1 on-chip input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1. Rev. 1.00 Sep. 21, 2006 Page 153 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.1.4 Pin Functions * P17/A7/PW7, P16/A6/PW6, P15/A5/PW5, P14/A4/PW4, P13/A3/PW3, P12/A2/PW2 The pin function is switched as shown below according to the combination of the OEn bit in PWOERA of PWM, the P1nDDR bit, and operating mode. Operating Mode P1nDDR OEn Pin Function Mode 1 -- -- A7 to A2 output pins 0 -- 0 Mode 2, 3 (EXPE = 1) 1 1 0 -- 0 Mode 2, 3 (EXPE = 0) 1 1 P17 to A7 to A2 PW7 to P17 to P17 to PW7 to P12 input output PW2 output P12 input P12 output PW2 pins pins pins pins pins output pins Note: n = 7 to 2 * P11/A1/PW1/PWX1 The pin function is switched as shown below according to the combination of the OE1 bit in PWOERA of PWM, the OEB bit in DACR of PWMX, the P11DDR bit, and operating mode. Operating Mode Mode 1 OEB P11DDR OE1 Pin Function -- -- -- A1 output pin 0 -- P11 input pin 0 A1 output pin Mode 2, 3 (EXPE = 1) 0 1 1 PW1 output pin 1 -- -- PWX1 output pin 0 -- P11 input pin 0 P11 output pin Mode 2, 3 (EXPE = 0) 0 1 1 PW1 output pin 1 -- -- PWX1 output pin * P10/A0/PW0/PWX0 The pin function is switched as shown below according to the combination of the OE0 bit in PWOERA of PWM, the OEA bit in DACR of PWMX, the P10DDR bit, and operating mode. Operating Mode Mode 1 OEA P10DDR OE0 Pin Function -- -- -- A0 output pin 0 -- P10 input pin 0 A0 output pin Mode 2, 3 (EXPE = 1) 0 1 1 PW0 output pin 1 -- -- PWX0 output pin 0 -- P10 input pin 0 P10 output pin Mode 2, 3 (EXPE = 0) 0 1 1 PW0 output pin 1 -- -- PWX0 output pin Rev. 1.00 Sep. 21, 2006 Page 154 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.1.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 8.2 summarizes the input pull-up MOS states. Table 8.2 Mode 1 2, 3 Input Pull-Up MOS States (Port 1) Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off [Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P1DDR = 0, and P1PCR = 1; otherwise off. Rev. 1.00 Sep. 21, 2006 Page 155 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.2 Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output pins, PWM output pins, and SCI_1 and IIC_1 I/O pins. Port 2 functions change according to the operating mode. Port 2 has an on-chip input pull-up MOS function that can be controlled by software. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) 8.2.1 Port 2 Data Direction Register (P2DDR) P2DDR specifies input or output for the pins of port 2 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In Mode 1: The corresponding port 2 pins are address outputs, regardless of the P2DDR setting. Modes 2 and 3 (EXPE = 1): The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. To ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. Modes 2 and 3 (EXPE = 0): The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1, and input ports when cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 156 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.2.2 Port 2 Data Register (P2DR) P2DR stores output data for port 2. Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. 8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 on-chip input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 2 and 3, the input pull-up MOS is turned on when a P2PCR bit is set to 1 in the input port state. Rev. 1.00 Sep. 21, 2006 Page 157 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.2.4 Pin Functions To ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. * P27/A15/PW15/SCK1 The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the C/A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR of SCI_1, the OE15 bit in PWOERB of PWM, the P27DDR bit, and operating mode. Operating Mode 1 Mode CKE1 C/A CKE0 P27DDR OE15 IOSE Pin Function -- -- -- -- -- -- A15 output pin 0 -- -- P27 input pin 0 A15 pin 0 1 P27 pin 0 1 1 -- PW15 pin 0 1 -- -- -- 0 1 -- -- -- -- 1 -- -- -- -- -- SCK1 input pin P27 input pin P27 pin PW15 pin 0 -- 0 0 1 1 -- SCK1 output pin SCK1 input pin 0 1 -- -- 0 1 -- -- -- 1 -- -- -- -- Mode 2, 3 (EXPE = 1) Mode 2, 3 (EXPE = 0) SCK1 output pin output output output output output * P26/A14/PW14/RxD1 The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the RE bit in SCR of SCI_1, the OE14 bit in PWOERB of PWM, the P26DDR bit, and operating mode. Operating Mode Mode 1 RE P26DDR OE14 IOSE Pin Function -- -- -- -- A14 output pin 0 -- -- P26 input pin 0 0 1 Mode 2, 3 (EXPE = 1) 0 1 1 -- 1 -- -- -- RxD1 input pin P26 input pin 0 -- 0 -- P26 PW14 output output pin pin RxD1 input pin Mode 2, 3 (EXPE = 0) 0 1 1 1 -- -- A14 P26 PW14 output output output pin pins pin Rev. 1.00 Sep. 21, 2006 Page 158 of 658 REJ09B0310-0100 Section 8 I/O Ports * P25/A13/PW13/TxD1 The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the TE bit in SCR of SCI_1, the OE13 bit in PWOERB of PWM, the P25DDR bit, and operating mode. Operating Mode Mode 1 TE P25DDR OE13 IOSE Pin Function -- -- -- -- A13 output pin 0 -- -- P25 input pin 0 0 1 Mode 2, 3 (EXPE = 1) 0 1 1 -- 1 -- -- -- TxD1 input pin P25 input pin 0 -- 0 -- P25 PW13 output output pin pin TxD1 input pin Mode 2, 3 (EXPE = 0) 0 1 1 1 -- -- A13 P25 PW13 output output output pin pin pin * P24/A12/PW12/SCL1 The pin function is switched as shown below according to the combination of the IOSE bit in SYSCR, the ICE bit in ICCR of IIC_1, the OE12 bit in PWOERB of PWM, the P24DDR bit, and operating mode. Operating Mode Mode 1 ICE P24DDR OE12 IOSE Pin Function -- -- -- -- A12 output pin 0 -- -- P24 input pin 0 0 1 Mode 2, 3 (EXPE = 1) 0 1 1 -- 1 -- -- -- P24 input pin 0 -- 0 -- P24 PW12 SCL1 output output I/O pin pin pin Mode 2, 3 (EXPE = 0) 0 1 1 1 -- -- A12 P24 PW12 SCL1 output output output I/O pin pin pin pin Rev. 1.00 Sep. 21, 2006 Page 159 of 658 REJ09B0310-0100 Section 8 I/O Ports * P23/A11/PW11/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1, the OE11 bit in PWOERB of PWM, the P23DDR bit, and operating mode. Operating Mode Mode 1 ICE P23DDR OE11 Pin Function -- -- -- A11 output pin 0 -- P23 input pin 0 A11 output pin Mode 2, 3 (EXPE = 1) 0 1 1 PW11 output pin 1 -- -- SDA1 I/O pin 0 -- P23 input pin 0 P23 output pin Mode 2, 3 (EXPE = 0) 0 1 1 PW11 output pin 1 -- -- SDA1 I/O pin * P22/A10/PW10, P21/A9/PW9, P20/A8/PW8 The pin function is switched as shown below according to the combination of the OEm bit in PWOERB of PWM, the P2nDDR bit, and operating mode. Operating Mode P2nDDR OEm Pin Function Mode 1 -- -- 0 -- 0 Mode 2, 3 (EXPE = 1) 1 1 0 -- 0 Mode 2, 3 (EXPE = 0) 1 1 A10 to A8 P22 to A10 to PW10 to P22 to P22 to PW10 to output P20 input A8 output PW8 output P20 input P20 output PW8 pins pins pins pins pins pins output pins Note: n = 2 to 0 m = 10 to 8 Rev. 1.00 Sep. 21, 2006 Page 160 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.2.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 8.3 summarizes the input pull-up MOS states. Table 8.3 Mode 1 2, 3 Input Pull-Up MOS States (Port 2) Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off [Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P2DDR = 0, and P2PCR = 1; otherwise off. Rev. 1.00 Sep. 21, 2006 Page 161 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.3 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus. Port 3 functions change according to the operating mode. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) 8.3.1 Port 3 Data Direction Register (P3DDR) P3DDR specifies input or output for the pins of port 3 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Modes 1, 2, and 3 (EXPE = 1) The input/output direction specified by P3DDR is ignored, and pins automatically function as data I/O pins. Modes 2 and 3 (EXPE = 0) The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 162 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.3.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. 8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 2 and 3 (when EXPE = 0), the input pull-up MOS is turned on when a P3PCR bit is set to 1 in the input port state. Rev. 1.00 Sep. 21, 2006 Page 163 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.3.4 Pin Functions * P37/D7, P36/D6, P35/D5, P34/D4, P33/D3, P32/D2, P31/D1, P30/D0 The pin function is switched as shown below according to the combination of the P3nDDR bit and operating mode. Operating Mode Mode 1, 2, 3 (EXPE = 1) P3nDDR Pin Function Note: n = 7 to 0 -- D7 to D0 input/output pins 0 P37 to P30 input pins Mode 2, 3 (EXPE = 0) 1 P37 to P30 output pins 8.3.5 Port 3 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 8.4 summarizes the input pull-up MOS states. Table 8.4 Mode Input Pull-Up MOS States (Port 3) Reset Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off 1, 2, 3 (EXPE = 1) Off 2, 3 (EXPE = 0) [Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P3DDR = 0, and P3PCR = 1; otherwise off. Rev. 1.00 Sep. 21, 2006 Page 164 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.4 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as external interrupt input pins, the A/D converter input pins, the IIC_0 I/O pins, the subclock input pins, bus control signal I/O pins, and the system clock () output pins. P47 is an NMOS push-pull output. SDA0 is an NMOS opendrain output, and has direct bus drive capability. Port 4 has the following registers. * * * * * * Port 4 data direction register (P4DDR) Port 4 data register (P4DR) Port 4 pull-up MOS control register (P4PCR) Port 4 noise canceller enable register (P4NCE) Port 4 noise canceller determine control register (P4NCMC) Port 4 noise canceller cycle setting register (P4NCCS) Rev. 1.00 Sep. 21, 2006 Page 165 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.4.1 Port 4 Data Direction Register (P4DDR) P4DDR specifies input or output for the pins of port 4 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial Value 0 1/0* 0 0 0 0 0 0 R/W W W W W W W W W Description P4DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3). Modes 1, 2, and 3 (EXPE = 1): Pin P47 functions as a bus control input (WAIT), the IIC_0 I/O pin (SDA0), or an I/O port, according to the wait mode setting. When P97 functions as an I/O port, it becomes an output port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0. Pin P46 functions as the output pin when P46DDR is set to 1, and as the subclock input (EXCL) or an input port when P96DDR is cleared to 0. Pins P45 to P43 automatically become bus control outputs (AS/IOS, WR, RD), regardless of the input/output direction indicated by P45DDR to P43DDR. Pins P42 to P40 become output ports when P42DDR to P40DDR are set to 1, and input ports when P42DDR to P40DDR are cleared to 0. Modes 2 and 3 (EXPE = 0): When the corresponding P4DDR bits are set to 1, pin P46 functions as the output pin and pins P47 and P45 to P40 become output ports. When P4DDR bits are cleared to 0, the corresponding pins become input ports. Note: * The initial value of P46DDR is 1 (mode 1) or 0 (modes 2 and 3). Rev. 1.00 Sep. 21, 2006 Page 166 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.4.2 Port 4 Data Register (P4DR) P4DR stores output data for the port 4 pins. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR * Initial Value 0 R/W R/W Description P4DR stores output data other than the bit 6 for the port 4 pins that are used as the general output port. If a port 4 read is performed while the P4DDR bits are set to 1, the P4DR values are read. If a port 4 read is performed while the P4DDR bits are cleared to 0, the pin states are read. Undefined* R/W 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Undefined value is determined depends on P46 pin state. 8.4.3 Port 4 Pull-Up MOS Control Register (P4PCR) P4PCR controls the on/off state of the input pull-up MOS for port 4 pins. Bit 7, 6 5 4 3 2 to 0 Bit Name P45PCR P44PCR P43PCR Initial Value All 0 0 0 0 All 0 R/W R/W R/W R/W R/W Reserved The initial value should not be changed. Description Reserved The initial value should not be changed. When the pins are in input state, the corresponding input pull-up MOS is turned on when a P4PCR bit is set to 1. Rev. 1.00 Sep. 21, 2006 Page 167 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.4.4 Port 4 Noise Canceller Enable Register (P4NCE) P4NCE enables or disables the noise cancel circuit at port 4 in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name P47NCE P46NCE P45NCE P44NCE P43NCE P42NCE P41NCE P40NCE Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Noise cancel circuit is enabled when P4NCE bit is set to 1, and the pin state is fetched in the P4DR in the sampling cycle set by the P4NCCS. 8.4.5 Port 4 Noise Canceller Mode Control Register (P4NCMC) P4NCMC controls whether 1 or 0 is expected for the input signal to port 4 in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name P47NCMC P46NCMC P45NCMC P44NCMC P43NCMC P42NCMC P41NCMC P40NCMC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 expected: 1 is stored in the port data register when 1 is input stably 0 expected: 0 is stored in the port data register when 0 is input stably Rev. 1.00 Sep. 21, 2006 Page 168 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.4.6 Port 4 Noise Cancel Cycle Setting Register (P4NCCS) P4NCCS controls the sampling cycles of the noise canceller. Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read data is undefined. The write value should always be 0. 2 1 0 P4NCCK2 P4NCCK1 P4NCCK0 0 0 0 R/W R/W R/W These bits set the sampling cycles of the noise canceller. When is 10 MHz 000: 001: 010: 011: 100: 101: 110: 111: 0.80 s 12.8 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 104.9 ms /2 /32 /8192 /16384 /32768 /65536 /131072 /262144 Undefined R/W 8.4.7 Pin Functions * P47/WAIT/SDA0 The pin function is switched as shown below according to the combination of operating mode, the WMS1 bit in WSCR, the ICE bit in ICCR of IIC_0, and the P47DDR bit. Operating Mode WMS1 ICE P47DDR Pin Function 0 0 1 Modes 1, 2, 3 (EXPE = 1) 0 1 -- 1 -- -- WAIT input pin 0 0 1 Modes 2, 3 (EXPE = 0) -- 1 -- P47 input P47 SDA0 I/O pin output pin pin P47 input P47 SDA0 I/O pin output pin pin Note: When this pin is set as the P47 output pin, it is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Rev. 1.00 Sep. 21, 2006 Page 169 of 658 REJ09B0310-0100 Section 8 I/O Ports * P46//EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P46DDR bit. P46DDR EXCLE Pin Function 0 P46 input pin 0 1 EXCL input pin 1 0 output pin Note: When this pin is used as the EXCL input pin, P46DDR should be cleared to 0. * P45/AS/IOS The pin function is switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and the P45DDR bit. Operating Mode P45DDR IOSE Pin Function 0 AS output pin Modes 1, 2, 3 (EXPE = 1) -- 1 IOS output pin Modes 2, 3 (EXPE = 0) 0 -- P45 input pin 1 -- P45 output pin * P44/WR The pin function is switched as shown below according to the combination of operating mode and the P44DDR bit. Operating Mode Modes 1, 2, 3 (EXPE = 1) P44DDR Pin Function -- WR output pin 0 P44 input pin Modes 2, 3 (EXPE = 0) 1 P44 output pin * P43/RD The pin function is switched as shown below according to the combination of operating mode and the P43DDR bit. Operating Mode Modes 1, 2, 3 (EXPE = 1) P43DDR Pin Function -- RD output pin 0 P43 input pin Modes 2, 3 (EXPE = 0) 1 P43 output pin Rev. 1.00 Sep. 21, 2006 Page 170 of 658 REJ09B0310-0100 Section 8 I/O Ports * P42/IRQ0 P42DDR Pin Function Note: * 0 P42 input pin IRQ0 input pin* When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. 1 P42 output pin * P41/IRQ1 P41DDR Pin Function Note: * 0 P41 input pin IRQ1 input pin* When the bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin. 1 P41 output pin * P40/IRQ2/ADTRG The pin function is switched as shown below according to the combination of the P40DDR bit. P40DDR Pin Function Note: * 0 P40 input pin IRQ2 input pin, ADTRG input pin* When the IRQ2E bit in IER is set to 1, this pin is used as the IRQ2 input pin. When both of the TRGS1 and TRGS0 bits in ADCR of the A/D converter are set to 1, this pin is used as the ADTRG input pin. 1 P40 output pin Rev. 1.00 Sep. 21, 2006 Page 171 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.5 Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_0 I/O pins, and the IIC_0 I/O pin. P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) 8.5.1 Port 5 Data Direction Register (P5DDR) P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis. Bit 7 to 3 2 1 0 Bit Name -- P52DDR P51DDR P50DDR Initial Value All 1 0 0 0 R/W -- W W W Description Reserved The initial value must not be changed. The corresponding port 5 pins are output ports when P5DDR bits are set to 1, and input ports when cleared to 0. As SCI_0 is initialized in software standby mode, the pin states are determined by the IIC_0 ICCR, P5DDR, and P5DR specifications. 8.5.2 Port 5 Data Register (P5DR) P5DR stores output data for port 5 pins. Bit 7 to 3 2 1 0 Bit Name -- P52DR P51DR P50DR Initial Value All 1 0 0 0 R/W -- R/W R/W R/W Description Reserved The initial value must not be changed. If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. Rev. 1.00 Sep. 21, 2006 Page 172 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.5.3 Pin Functions * P52/SCK0/SCL0 The pin function is switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_0, the C/A bit in SMR of SCI_0, the ICE bit in ICCR of IIC_0, and the P52DDR bit. ICE CKE1 C/A CKE0 P52DDR Pin Function 0 P52 input pin 0 1 P52 output pin 0 1 -- 0 1 -- -- 0 1 -- -- -- SCK0 input pin 1 0 0 0 -- SCL0 I/O pin SCK0 output SCK0 output pin pin Note: When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0 and bit C/A in SMR of SCI0 must all be cleared to 0. SCL0 is an NMOS open-drain output, and has direct bus drive capability. When set as the P52 output pin or SCK0 output pin, this pin is an NMOS push-pull output. * P51/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P51DDR bit. RE P51DDR Pin Function 0 P51 input pin 0 1 P51 output pin 1 -- RxD0 input pin * P50/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P50DDR bit. TE P50DDR Pin Function 0 P50 input pin 0 1 P50 output pin 1 -- TxD0 output pin Rev. 1.00 Sep. 21, 2006 Page 173 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.6 Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as the noise cancel pins and I/O pins for FRT, TMR_0, TMR_1, TMR_X, and TMR_Y. Port 6 has the following registers. * * * * * Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Port 6 noise canceller enable register (P6NCE) Port 6 noise canceller mode control register (P6NCMC) Port 6 noise cancel cycle setting register (P6NCCS) Port 6 Data Direction Register (P6DDR) 8.6.1 P6DDR specifies input or output for the pins of port 6 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 6 pins are output ports when P6DDR bits are set to 1, and input ports when cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 174 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.6.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. 8.6.3 Port 6 Noise Canceller Enable Register (P6NCE) P6NCE specifies enable or disable for noise cancel circuit for the pins of port 6 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P67NCE P66NCE P65NCE P64NCE P63NCE P62NCE P61NCE P60NCE Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Noise cancel circuit is enabled when P6NCCS bit is set to 1, and the pin state is fetched in the P6DR in the sampling cycle set by the P6NCCS. Rev. 1.00 Sep. 21, 2006 Page 175 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.6.4 Port 6 Noise Canceller Mode Control Register (P6NCMC) P6NCMC controls whether 1 or 0 is expected for the input signal to port 6 in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name P67NCMC P66NCMC P65NCMC P64NCMC P63NCMC P62NCMC P61NCMC P60NCMC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 expected: 1 is stored in the port data register when 1 is input stably 0 expected: 0 is stored in the port data register when 0 is input stably 8.6.5 Port 6 Noise Cancel Cycle Setting Register (P6NCCS) P6NCCS controls the sampling cycles of the noise canceller. Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read data is undefined. The write value should always be 0. 2 1 0 P6NCCK2 P6NCCK1 P6NCCK0 0 0 0 R/W R/W R/W These bits set the sampling cycles of the noise canceller. When is 10 MHz 000: 001: 010: 011: 100: 101: 110: 111: 0.80 s 12.8 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 104.9 ms /2 /32 /8192 /16384 /32768 /65536 /131072 /262144 Undefined R/W Rev. 1.00 Sep. 21, 2006 Page 176 of 658 REJ09B0310-0100 Section 8 I/O Ports /2, /32, /8192, /16384, /32768, /65536, /131072, /262144 Sampling clock selection t Matching detection curcuit Pin input Latch Latch Latch Latch Port data register t Interrupt input Keyboard input Sampling clock Figure 8.1 Noise Cancel Circuit P6n input 1 expected P6n input 0 expected P6n input (n = 7 to 0) Figure 8.2 Conceptual Diagram of Noise Cancel Operation Rev. 1.00 Sep. 21, 2006 Page 177 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.6.6 Pin Functions * P67/IRQ3/TMOX/TMO1 The pin function is switched as shown below according to the OS3 to OS0 bits in TCSR of TMR_1 and TMR_X and the P67DDR bit. When the IRQ3E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ3 input pin. OS3 to OS0 (TMR_X) OS3 to OS0 (TMR_1) P67DDR Pin Function 0 P67 input pin All 0 1 P67 output pin IRQ3 input pin All 0 Not all 0 -- TMO1 output pin Not all 0 -- -- TMOX output pin * P66/FTOB/TMRI1 The pin function is switched as shown below according to the combination of the OEB bit in TOCR of FRT and the P66DDR bit. When the CCLR1 and CCLR0 bits in TCR of TMR_1 are both set to 1, this pin can be used as the TMRI1 input pin. OEB P66DDR Pin Function 0 P66 input pin 0 1 P66 output pin TMRI1 input pin 1 -- FTOB output pin * P65/FTID/TMCI1 The pin function is switched as shown below according to the P65DDR bit. When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin. When the external clock is selected with the CKS2 to CKS0 bits in TCR of TMR_1, this pin can be used as the TMCI1 input pin. P65DDR Pin Function 0 P65 input pin 1 P65 output pin FTID input pin/TMCI1 input pin Rev. 1.00 Sep. 21, 2006 Page 178 of 658 REJ09B0310-0100 Section 8 I/O Ports * P64/FTIC/TMO0 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_0 and the P64DDR bit. When the ICICE bit in TIER of FRT is set to 1, this pin can be used as the FTIC input pin. OS3 to OS0 P64DDR Pin Function 0 P64 input pin All 0 1 P64 output pin FTIC input pin Not all 0 -- TMO0 output pin * P63/FTIB/TMRI0 The pin function is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin is used as the FTIB input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_0 are both set to 1, this pin can be used as the TMRI0 input pin. P63DDR Pin Function 0 P63 input pin 1 P63 output pin FTIB input pin/TMRI0 input pin * P62/FTIA/TMIY The pin function is switched as shown below according to the P62DDR bit. When the ICIAE bit in TIER of FRT is set to 1, this pin can be used as the FTIA input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_Y are both set to 1, this pin can be used as the TMIY (TMRIY) input pin. P62DDR Pin Function 0 P62 input pin 1 P62 output pin FTIA input pin/TMIY input pin Rev. 1.00 Sep. 21, 2006 Page 179 of 658 REJ09B0310-0100 Section 8 I/O Ports * P61/FTOA/TMOY The pin function is switched as shown below according to the combination of the OEA bit in TOCR of FRT, the OS3 to OS0 bits in TCSR of TMR_Y, and the P61DDR bit. OS3 to OS0 OEA P61DDR Pin Function 0 P61 input pin 0 1 P61 output pins All 0 1 -- FTOA output pin Not all 0 -- -- TMOY output pin * P60/FTCI/TMCI0/TMIX The pin function is switched as shown below according to the P60DDR bit. When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can be used as the FTCI input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_X are both set to 1, this pin can be used as the TMIX (TMRIX) input pin. When the external clock is selected with the CKS2 to CKS0 bits in TCR of TMR_0, this pin can be used as the TMCI0 input pin. P60DDR Pin Function 0 P60 input pin 1 P60 output pin FTCI input pin/TMCI0 input pin/TMIX input pin Rev. 1.00 Sep. 21, 2006 Page 180 of 658 REJ09B0310-0100 Section 8 I/O Ports 8.7 Port 7 Port 7 is an 8-bit input port. Port 7 pins also function as the interrupt input pins, A/D converter analog input pins, TCM_0 input pin, and TCM_1 input pin. Port 7 has the following register. * Port 7 input data register (P7PIN) 8.7.1 Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN * Initial Value R/W Description When this register is read, the pin states are read. Undefined* R Undefined* R Undefined* R Undefined* R Undefined* R Undefined* R Undefined* R Undefined* R The initial value is determined in accordance with the pin states of P77 to P70. 8.7.2 Pin Functions * P77/AN7/IRQ7/TCMCKI0 When the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin. When the external clock is selected with the CKS2 to CKS0 bits in TCMCR_0 of TCM_0, this pin can be used as the TCMCKI0 input pin. Pin Function P77 input pin/AN7 input pin/IRQ7 input pin/TCMCKI0 input pin Rev. 1.00 Sep. 21, 2006 Page 181 of 658 REJ09B0310-0100 Section 8 I/O Ports * P76/AN6/IRQ6/TCMCYI0 When the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ6 input pin. When the TCMIPE bit in TCMIER_0 of TCM_0 is set to 1, this pin can be used as the TCMCYI0 input pin. Pin Function P76 input pin/AN6 input pin/IRQ6 input pin/TCMCYI0 input pin * P75/AN5/IRQ5/TCMCYI1 When the IRQ5E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ5 input pin. When the external clock is selected with the CKS2 to CKS0 bits in TCMCR_1 of TCM_1, this pin can be used as the TCMCKI1 input pin. Pin Function P75 input pin/AN5 input pin/IRQ5 input pin/TCMCKI1 input pin * P74/AN4/IRQ4/TCMCYI1 When the IRQ4E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ4 input pin. When the TCMIPE bit in TCMIER_1 of TCM_1 is set to 1, this pin can be used as the TCMCYI1 input pin. Pin Function P74 input pin/AN4 input pin/IRQ4 input pin/TCMCYI1 input pin * P73/AN3, P72/AN2, P71/AN1, P70/AN0 Pin Function Note: n = 3 to 0 P7n input pin/ANn input pin Rev. 1.00 Sep. 21, 2006 Page 182 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) Section 9 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. 9.1 Features * Operable at a maximum carrier frequency of 1.25 MHz using pulse division (at 20 MHz operation) * Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) * Direct or inverted PWM output, and PWM output enable/disable control PWM0800A_010020020700 Rev. 1.00 Sep. 21, 2006 Page 183 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) Figure 9.1 shows a block diagram of the PWM timer. P10/PW0 P11/PW1 P12/PW2 P13/PW3 P14/PW4 P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 P23/PW11 P24/PW12 P25/PW13 P26/PW14 P27/PW15 Port/PWM output control Comparator 0 Comparator 1 Comparator 2 Comparator 3 Comparator 4 Comparator 5 Comparator 6 Comparator 7 Comparator 8 Comparator 9 Comparator 10 Comparator 11 Comparator 12 Comparator 13 Comparator 14 Comparator 15 PWDR0 PWDR1 PWDR2 PWDR3 PWDR4 PWDR5 Module data bus Bus interface PWDR6 PWDR7 PWDR8 PWDR9 PWDR10 PWDR11 PWDR12 PWDR13 PWDR14 PWDR15 Internal data bus PWDPRB PWOERB P2DDR P2DR PWDPRA PWOERA P1DDR P1DR TCNT Select clock PWSL PCSR [Legend] PWSL: PWDR: PWDPRA: PWDPRB: PWOERA: PWOERB: PCSR: P1DDR: P2DDR: P1DR: P2DR: PWM register select PWM data register PWM data polarity register A PWM data polarity register B PWM output enable register A PWM output enable register B Peripheral clock select register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register /2 /4 /8 /16 Internal clock Figure 9.1 Block Diagram of PWM Timer Rev. 1.00 Sep. 21, 2006 Page 184 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.2 Input/Output Pin Table 9.1 shows the PWM output pins. Table 9.1 Name PWM output 15 to 0 Pin Configuration Abbreviation PW15 to PW0 I/O Output Function PWM timer pulse output 15 to 0 9.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR). * * * * * * * PWM register select (PWSL) PWM data registers 0 to 15 (PWDR0 to PWDR15) PWM data polarity register A (PWDPRA) PWM data polarity register B (PWDPRB) PWM output enable register A (PWOERA) PWM output enable register B (PWOERB) Peripheral clock select register (PCSR) Rev. 1.00 Sep. 21, 2006 Page 185 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit 7 6 Bit Name PWCKE PWCKS Initial Value 0 0 R/W R/W R/W Description PWM Clock Enable PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 9.2. The resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations. Resolution (minimum pulse width) = 1/internal clock frequency PWM conversion period = resolution x 256 Carrier frequency = 16/PWM conversion period With a 20 MHz system clock (), the resolution, PWM conversion period, and carrier frequency are as shown in table 9.3. 5 4 -- -- 1 0 R R Reserved This bit is always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 21, 2006 Page 186 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) Bit 3 2 1 0 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Register Select These bits select the PWM data register. 0000: PWDR0 selected 0001: PWDR1 selected 0010: PWDR2 selected 0011: PWDR3 selected 0100: PWDR4 selected 0101: PWDR5 selected 0110: PWDR6 selected 0111: PWDR7 selected 1000: PWDR8 selected 1001: PWDR9 selected 1010: PWDR10 selected 1011: PWDR11 selected 1100: PWDR12 selected 1101: PWDR13 selected 1110: PWDR14 selected 1111: PWDR15 selected Table 9.2 Internal Clock Selection PCSR PWCKB -- -- 0 PWCKA -- -- 0 1 1 0 1 Description Clock input is disabled (system clock) is selected /2 is selected /4 is selected /8 is selected /16 is selected (Initial value) PWSL PWCKE 0 1 PWCKS -- 0 1 Rev. 1.00 Sep. 21, 2006 Page 187 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) Table 9.3 Resolution, PWM Conversion Period and Carrier Frequency when = 20 MHz Resolution 50 ns 100 ns 200 ns 400 ns 800 ns PWM Conversion Period 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s Carrier Frequency 1250 kHz 625 kHz 312.5 kHz 156.3 kHz 78.1 kHz Internal Clock Frequency /2 /4 /8 /16 9.3.2 PWM Data Registers (PWDR0 to PWDR15) PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers. Each PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The lower four bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output should be used. PWDR0 to PWDR15 are initialized to H'00. Rev. 1.00 Sep. 21, 2006 Page 188 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.3.3 PWM Data Polarity Registers A and B (PWDPRA, PWDPRB) Each PWDPR selects the PWM output phase. * PWDPRA Bit 7 6 5 4 3 2 1 0 Bit Name OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 7 to 0 These bits select the PWM output phase. Bits OS7 to OS0 correspond to outputs PW7 to PW0. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) * PWDPRB Bit 7 6 5 4 3 2 1 0 Bit Name OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 15 to 8 These bits select the PWM output phase. Bits OS15 to OS8 correspond to outputs PW15 to PW8. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) Rev. 1.00 Sep. 21, 2006 Page 189 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.3.4 PWM Output Enable Registers A and B (PWOERA, PWOERB) Each PWOER switches between PWM output and port output. * PWOERA Bit 7 6 5 4 3 2 1 0 Bit Name OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 7 to 0 These bits, together with P1DDR, specify the P1n/PWn pin state. Bits OE7 to OE0 correspond to outputs PW7 to PW0. P1nDDR OEn: Pin state 0X: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) [Legend] X: Don't care * PWOERB Bit 7 6 5 4 3 2 1 0 Bit Name OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 15 to 8 These bits, together with P2DDR, specify the P2n/PWn pin state. Bits OE15 to OE8 correspond to outputs PW15 to PW8. P2nDDR OEn: Pin state 0X: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) [Legend] X: Don't care Rev. 1.00 Sep. 21, 2006 Page 190 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output. The corresponding pin can be set as port output in single-chip mode (PW15 to PW0) or when IOSE = 1 (PW15 to PW12) in SYSCR in extended mode with on-chip ROM. Otherwise, it should be noted that an address bus is output to the corresponding pin. DR data is output when the corresponding pin is used as port output. A value corresponding to PWM 256/256 output is determined by the OE bit, so the value should have been set to DR beforehand. 9.3.5 Peripheral Clock Select Register (PCSR) PCSR selects the PWM input clock. Bit 7 6 5 4 3 2 1 Bit Name -- -- PWCKXB PWCKXA -- PWCKB PWCKA All 0 0 0 Initial Value 0 0 R/W R/W R/W R/W R/W R R/W R/W Description Reserved The initial value should not be changed. PWMX Clock Select For details, see section 10.3.4, Peripheral Clock Select Register (PCSR). Reserved The initial value should not be changed. PWM Clock Select B, A Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to the clock counter. For details, see table 9.2. PWMX Clock Select For details, see section 10.3.4, Peripheral Clock Select Register (PCSR). 0 PWCKXC 0 R/W Rev. 1.00 Sep. 21, 2006 Page 191 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse. Table 9.4 Upper 4 Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Duty Cycle of Basic Pulse Basic Pulse Waveform (Internal) 0123456789ABCDEF0 Rev. 1.00 Sep. 21, 2006 Page 192 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 shows the positions of the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional pulse timing. Table 9.5 Position of Pulses Added to Basic Pulses Basic Pulse No. Lower 4 Bits 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No additional pulse Resolution width With additional pulse Basic pulse Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000) Rev. 1.00 Sep. 21, 2006 Page 193 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.4.1 PWM Setting Example (Pulse Division System) 1-conversion cycle PWDR setting example H'7F 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Duty cycle 127/256 Basic waveform 112 pulses Additiona pulse 15 pulses H'80 128/256 128 pulses 0 pulses H'81 129/256 128 pulses 1 pulse H'82 130/256 128 pulses 2 pulses : Pulse added Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of dudty cycle as low ripple wave form. Figure 9.3 Example of PWM Setting 9.4.2 Diagram of PWM Used as D/A Converter Figure 9.4 shows the diagram example when using the PWM pulse as the D/A converter. Analog signal with low ripple can be generated by connecting the low pass filter. Resistor : 120 k Capacitor : 0.1 F This LSI Low pass filter Reference value Figure 9.4 Example when PWM is Used as D/A Converter Rev. 1.00 Sep. 21, 2006 Page 194 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) 9.5 9.5.1 Usage Note Module Stop Mode Setting PWM operation can be enabled or disabled using the module stop control register. The initial setting is for PWM operation to be halted. Register access is enabled by canceling the module stop mode. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 195 of 658 REJ09B0310-0100 Section 9 8-Bit PWM Timer (PWM) Rev. 1.00 Sep. 21, 2006 Page 196 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) Section 10 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 10.1 Features * Division of pulse into multiple base cycles to reduce ripple * Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Sixteen operation clocks (by combination of eight resolution settings and two base cycle settings) Figure 10.1 shows a block diagram of the PWM (D/A) module. Internal clock /2, /64, /128, /256, /1024, /4096, /16384 Clock Base cycle compare match A PWX0 PWX1 Fine-adjustment pulse addition A Internal data bus PCSR Select clock Bus interface Comparator A Comparator B DADRA DADRB Base cycle compare match B Fine-adjustment pulse addition B Control logic Base cycle overflow DACNT DACR [Legend] DACR: PWMX D/A control register (6 bits) DADRA: PWMX D/A data register A (15 bits) DADRB: PWMX D/A data register B (15 bits) DACNT: PWMX D/A counter (14 bits) PCSR: Peripheral clock select register Module data bus Figure 10.1 PWMX (D/A) Block Diagram PWM1420A_000020020300 Rev. 1.00 Sep. 21, 2006 Page 197 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.2 Input/Output Pins Table 10.1 lists the PWMX (D/A) module input and output pins. Table 10.1 Pin Configuration Name PWMX output pin 0 PWMX output pin 1 Abbreviation I/O PWX0 PWX1 Output Output Function PWMX output of channel A PWMX output of channel B 10.3 Register Descriptions The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). For details on the module stop control register, see section 22.1.3, Module Stop Control Register H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, and MSTPCRB). * * * * * PWMX (D/A) counter (DACNT) PWMX (D/A) data register A (DADRA) PWMX (D/A) data register B (DADRB) PWMX (D/A) control register (DACR) Peripheral clock select register (PCSR) Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. Rev. 1.00 Sep. 21, 2006 Page 198 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper 2-bit counter. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 10.4, Bus Master Interface. DACNTH Bit (CPU): Bit (counter): 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 DACNTL 4 11 3 12 2 13 1 0 REGS * DACNTH Bit 7 to 0 Bit Name Initial Value R/W R/W Description Upper Up-Counter DACNT7 to All 0 DACNT0 * DACNTL Bit 7 to 2 1 0 Bit Name Initial Value R/W R/W R R/W Description Lower Up-Counter Reserved Always read as 1 and cannot be modified. REGS 1 Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed DACNT 8 to All 0 DACNT 13 1 Rev. 1.00 Sep. 21, 2006 Page 199 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 10.4, Bus Master Interface. * DADRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 The range of DA13 to DA0: H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 The range of DA13 to DA0: H'0040 to H'3FFF 0 1 R Reserved Always read as 1 and cannot be modified. Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with DACNT12 and DACNT13 of DACNT. Rev. 1.00 Sep. 21, 2006 Page 200 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) * DADRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DA13 to DA0 range = H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 DA13 to DA0 range = H'0040 to H'3FFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with DACNT12 and DACNT13 of DACNT. Rev. 1.00 Sep. 21, 2006 Page 201 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit 7 6 Bit Name PWME Initial Value 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5 4 3 OEB 1 1 0 R R R/W Reserved Always read as 1 and cannot be modified. Output Enable B Enables or disables output on PWMX (D/A) channel B. 0: PWMX (D/A) channel B output (at the PWX1 output pin) is disabled 1: PWMX (D/A) channel B output (at the PWX1 output pin) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWMX (D/A) channel A. 0: PWMX (D/A) channel A output (at the PWX0 output pin) is disabled 1: PWMX (D/A) channel A output (at the PWX0 output pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWMX (D/A) output. 0: Direct PWMX (D/A) output 1: Inverted PWMX (D/A) output 0 CKS 0 R/W Clock Select Selects the PWMX (D/A) resolution. Eight kinds of resolution can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2, x 64, x 128, x 256, x 1024, x 4096, and x 16384. Rev. 1.00 Sep. 21, 2006 Page 202 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Bit 7 6 5 4 Bit Name PWCKXB PWCKXA Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. PWMX clock select These bits select a clock cycle with the CKS bit of DACR of PWMX being 1. See table 10.2. 3 2 1 0 PWCKB PWCKA PWCKXC 0 0 0 0 R/W R/W R/W R/W Reserved The initial value should not be changed. PWM clock select B, A See section 9.3.5, Peripheral Clock Select Register (PCSR). PWMX clock select This bit selects a clock cycle with the CKS bit of DACR of PWMX being 1. See table 10.2. Table 10.2 Clock Select of PWMX PWCKXC 0 0 0 0 1 1 1 1 PWCKXB 0 0 1 1 0 0 1 1 PWCKXA 0 1 0 1 0 1 0 1 Resolution (T) Operates on the system clock cycle (tcyc) x 2 Operates on the system clock cycle (tcyc) x 64 Operates on the system clock cycle (tcyc) x 128 Operates on the system clock cycle (tcyc) x 256 Operates on the system clock cycle (tcyc) x 1024 Operates on the system clock cycle (tcyc) x 4096 Operates on the system clock cycle (tcyc) x 16384 Setting prohibited Rev. 1.00 Sep. 21, 2006 Page 203 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. * Write When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. * Read When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Rev. 1.00 Sep. 21, 2006 Page 204 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) Table 10.3 Reading/Writing to 16-bit Registers Read Register DADRA, DADRB DACNT Word O O Byte O x Word O O Write Byte x x [Legend] O: Enabled access. Word-unit access includes accessing byte sequentially, first upper byte, and then lower byte. x: The result of the access in the unit cannot be guaranteed. (a) Write to upper byte Module data bus Bus interface CPU [H'AA] Upper byte TEMP [H'AA] DACNTH [ ] (b) Write to lower byte DACNTL [ ] CPU [H'57] Lower byte Module data bus Bus interface TEMP [H'AA] DACNTH [H'AA] DACNTL [H'57] Figure 10.2 (1) DACNT Access Operation (1) [CPU DACNT(H'AA57) Writing] Rev. 1.00 Sep. 21, 2006 Page 205 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) (a) Read upper byte Module data bus Bus interface CPU [H'AA] Upper byte TEMP [H'AA] DACNTH [ ] (b) Read lower byte DACNTL [ ] CPU [H'57] Lower byte Module data bus Bus interface TEMP [H'AA] DACNTH [H'AA] DACNTL [H'57] Figure 10.2 (2) DACNT Access Operation (2) [DACNT CPU(H'AA57) Reading] Rev. 1.00 Sep. 21, 2006 Page 206 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.5 Operation A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 10.4 and 10.5 show the types of waveform output available. 1 conversion cycle (T x 214 (= 16384)) tf Base cycle (T x 64 or T x 256) tL T: Resolution TL = tLn (OS = 0) n=1 m (When CFS = 0, m = 256 When CFS = 1, m = 64) Figure 10.3 PWMX (D/A) Operation Table 10.4 summarizes the relationships between the CKS and CFS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR contain at least a certain minimum value. The relationship between the OS bit and the output waveform is shown in figures 10.4 and 10.5. Rev. 1.00 Sep. 21, 2006 Page 207 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) Table 10.4 Settings and Operation (Examples when = 20 MHz) PCSR PWCKX0 PWCKX1 C B A Resolution T CK (s) 0 0.05 Base CFS Cycle 0 3.2 (s) /312.5kHz 1 12.8 (s) () 0 0 0 1 0.1 0 /78.1kHz 6.4 (s) /156.2kHz 1 25.6 (s) (/2) 0 0 1 1 3.2 0 /39.1kHz 204.8 (s) /4.9kHz 1 819.2 (s) (/64) 0 1 0 1 6.4 0 /1.2kHz 409.6 (s) /2.4kHz 1 1638.4 (s) (/128) /610.4kHz 104.9 (ms) 52.4 (ms) 1.64 (ms) Conversion Cycle 819.2 (s) TL/TH (OS = 0/OS = 1) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Accuracy DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA0 Bit Data Conversion Cycle* 819.2 s 204.8 s 51.2 s 819.2 s 204.8 s 51.2 s 1638.4 s 409.6 s 102.4 s 1638.4 s 409.6 s 102.4 s 52.4 ms 13.1 ms 3.3 ms 52.4 ms 13.1 ms 3.3 ms 104.9 ms 26.2 ms 6.6 ms 104.9 ms 26.2 ms 6.6 ms Fixed DADR Bits Rev. 1.00 Sep. 21, 2006 Page 208 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) PCSR PWCKX0 PWCKX1 C 0 B 1 A 1 Resolution T CKS (s) 1 12.8 Base CFS Cycle 0 819.2 (s) /1.2kHz 1 3276.8 (s) (/256) 1 0 0 1 51.2 0 /305.2kHz 3.3 (ms) /305.2Hz 1 13.1 (ms) (/1024) 1 0 1 1 204.8 0 /76.3Hz 13.1 (ms) /76.3Hz 1 52.4 (ms) (/4096) 1 1 0 1 496.48 0 /19.1Hz 52.4 (ms) /19.1Hz 1 209.7 (ms) (/16384) 1 1 1 1 Setting prohibited /4.8Hz 8.13 (s) 2.03 (s) 838.9 (ms) Conversion Cycle 209.7 (ms) TL/TH (OS = 0/OS = 1) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Fixed DADR Bits Bit Data Accuracy DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA0 Conversion Cycle* 209.7 ms 52.4 ms 13.1 ms 209.7 ms 52.4 ms 13.1 ms 838.9 ms 209.7 ms 52.4 ms 838.9 ms 209.7 ms 52.4 ms 3.4 s 838.9 ms 209.7 ms 3.4 s 838.9 ms 209.7 ms 13.4 s 3.4 s 838.9 ms 13.4 s 3.4 s 838.9 ms Note: * Indicates the conversion cycle when specific DA3 to DA0 bits are fixed. Rev. 1.00 Sep. 21, 2006 Page 209 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tL1 tL2 tL3 tL255 tL256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) x 256] Figure 10.4 Output Waveform (OS = 0, DADR corresponds to TL) Rev. 1.00 Sep. 21, 2006 Page 210 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tH1 tH2 tH3 tH255 tH256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) x 256] Figure 10.5 Output Waveform (OS = 1, DADR corresponds to TH) An example of the additional pulses when CFS = 1 (base cycle = resolution (T) x 256) and OS = 1 (inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0) determine the locations of the additional pulses as shown in figure 10.6. Table 10.5 lists the locations of the additional pulses. DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 Duty cycle of base pulse Location of additional pulses Figure 10.6 D/A Data Register Configuration when CFS = 1 In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 10.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 x (T). Rev. 1.00 Sep. 21, 2006 Page 211 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 10.5. Thus, an additional pulse of 1/256 x (T) is to be added to the base pulse. 1 conversion cycle Base cycle No. 0 Base cycle No. 1 Base cycle No. 63 Base pulse High width: 2/256 x (T) Base pulse 2/256 x (T) Additional pulse output location Additional pulse 1/256 x (T) Figure 10.7 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) x 64), the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above. Rev. 1.00 Sep. 21, 2006 Page 212 of 658 REJ09B0310-0100 Base pulse No. Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) Lower 6 bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Section 10 14-Bit PWM Timer (PWMX) Rev. 1.00 Sep. 21, 2006 Page 213 of 658 REJ09B0310-0100 Section 10 14-Bit PWM Timer (PWMX) 10.6 10.6.1 Usage Notes Module Stop Mode Setting PWMX operation can be enabled or disabled by using the module stop control register. In the initial state, PWMX operation is disabled. Register access is enabled by clearing module stop mode. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 214 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Section 11 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 11.1 Features * Selection of four clock sources One of the three internal clocks (/2, /8, or /32), or an external clock input can be selected (enabling use as an external event counter). * Two independent comparators Two independent waveforms can be output. * Four independent input capture channels The rising or falling edge can be selected. Buffer modes can be specified. * Counter clearing The free-running counters can be cleared on compare-match A. * Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM x 2, enabling input capture operations in this interval to be restricted. Figure 11.1 shows a block diagram of the FRT. TIM8FR1A_000020020300 Rev. 1.00 Sep. 21, 2006 Page 215 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) External clock Internal clock FTCI Clock selector /2 /8 /32 Clock OCRAR/F OCRA Compare-match A Bus interface FTOA FTOB FTIA FTIB FTIC FTID Input capture Overflow Module data bus Comparator A Internal data bus FRC Clear Compare-match B Control logic Comparator B OCRB ICRA ICRB ICRC ICRD Comparator M Compare-match M x1 x2 OCRDM TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt signal [Legend] OCRA, OCRB: Output compare register A, B (16-bit) OCRAR,OCRAF: Output compare register AR, AF (16-bit) OCRDM: Output compare register DM (16-bit) FRC: Free-running counter (16-bit) ICRA to ICRD: Input capture registers A to D (16-bit) TCSR: Timer control/status register (8-bit) TIER: Timer interrupt enable register (8-bit) TCR: Timer control register (8-bit) TOCR: Timer output compare control register (8-bit) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer Rev. 1.00 Sep. 21, 2006 Page 216 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.2 Input/Output Pins Table 11.1 lists the FRT input and output pins. Table 11.1 Pin Configuration Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input 11.3 Register Descriptions The FRT has the following registers. * * * * * * * * * * * * * * Free-running counter (FRC) Output compare register A (OCRA) Output compare register B (OCRB) Input capture register A (ICRA) Input capture register B (ICRB) Input capture register C (ICRC) Input capture register D (ICRD) Output compare register AR (OCRAR) Output compare register AF (OCRAF) Output compare register DM (OCRDM) Timer interrupt enable register (TIER) Timer control/status register (TCSR) Timer control register (TCR) Timer output compare control register (TOCR) Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Register selection is controlled by the ICRS bit in TOCR. Rev. 1.00 Sep. 21, 2006 Page 217 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 11.3.2 Output Compare Registers A and B (OCRA and OCRB) The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF. 11.3.3 Input Capture Registers A to D (ICRA to ICRD) The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is transferred to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then transferred to the buffer register ICRC. When IEDGA and IEDGC bits in TCR are set to different values, both rising and falling edges can be specified as the change of the external input signal. When IEDGA and IEDGC are set to the same value, either rising edge or falling edge can be specified as the change of the external input signal. To ensure input capture, the input capture pulse width should be at least 1.5 system clocks () for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (). Rev. 1.00 Sep. 21, 2006 Page 218 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000. 11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When using the OCRA automatic addition function, do not select internal clock /2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF. 11.3.5 Output Compare Register DM (OCRDM) OCRDM is a 16-bit readable/writable register in which the upper eight bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while the ICRDMS bit is set to 1. OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is initialized to H'0000. Rev. 1.00 Sep. 21, 2006 Page 219 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit 7 Bit Name ICIAE Initial Value 0 R/W R/W Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled 6 ICIBE 0 R/W Input Capture Interrupt B Enable Selects whether to enable input capture interrupt B request (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. 0: ICIB requested by ICFB is disabled 1: ICIB requested by ICFB is enabled 5 ICICE 0 R/W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. 0: ICIC requested by ICFC is disabled 1: ICIC requested by ICFC is enabled 4 ICIDE 0 R/W Input Capture Interrupt D Enable Selects whether to enable input capture interrupt D request (ICID) when input capture flag D (ICFD) in TCSR is set to 1. 0: ICID requested by ICFD is disabled 1: ICID requested by ICFD is enabled 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled Rev. 1.00 Sep. 21, 2006 Page 220 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Bit 2 Bit Name OCIBE Initial Value 0 R/W R/W Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled 0 1 R Reserved This bit is always read as 1 and cannot be modified. 11.3.7 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Bit 7 Bit Name ICFA Initial Value 0 R/W Description R/(W)* Input Capture Flag A This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFA when ICFA = 1, then write 0 to ICFA Rev. 1.00 Sep. 21, 2006 Page 221 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Bit 6 Bit Name ICFB Initial Value 0 R/W Description R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] Read ICFB when ICFB = 1, then write 0 to ICFB 5 ICFC 0 R/(W)* Input Capture Flag C This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin, ICFC is set but data is not transferred to ICRC. In buffer operation, ICFC can be used as an external interrupt signal by setting the ICICE bit to 1. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFC when ICFC = 1, then write 0 to ICFC 4 ICFD 0 R/(W)* Input Capture Flag D This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of an input capture signal specified by the IEDGD bit at the FTID input pin, ICFD is set but data is not transferred to ICRD. In buffer operation, ICFD can be used as an external interrupt signal by setting the ICIDE bit to 1. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFD when ICFD = 1, then write 0 to ICFD Rev. 1.00 Sep. 21, 2006 Page 222 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Bit 3 Bit Name OCFA Initial Value 0 R/W Description R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB 1 OVF 0 R/(W)* Overflow Flag This status flag indicates that the FRC has overflowed. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF 0 CCLRA 0 R/W Counter Clear A This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared at compare-match A Note: * Only 0 can be written to clear the flag. Rev. 1.00 Sep. 21, 2006 Page 223 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit 7 Bit Name IEDGA Initial Value 0 R/W R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA). 0: Capture on the falling edge of FTIA 1: Capture on the rising edge of FTIA 6 IEDGB 0 R/W Input Edge Select B Selects the rising or falling edge of the input capture B signal (FTIB). 0: Capture on the falling edge of FTIB 1: Capture on the rising edge of FTIB 5 IEDGC 0 R/W Input Edge Select C Selects the rising or falling edge of the input capture C signal (FTIC). 0: Capture on the falling edge of FTIC 1: Capture on the rising edge of FTIC 4 IEDGD 0 R/W Input Edge Select D Selects the rising or falling edge of the input capture D signal (FTID). 0: Capture on the falling edge of FTID 1: Capture on the rising edge of FTID 3 BUFEA 0 R/W Buffer Enable A Selects whether ICRC is to be used as a buffer register for ICRA. 0: ICRC is not used as a buffer register for ICRA 1: ICRC is used as a buffer register for ICRA 2 BUFEB 0 R/W Buffer Enable B Selects whether ICRD is to be used as a buffer register for ICRB. 0: ICRD is not used as a buffer register for ICRB 1: ICRD is used as a buffer register for ICRB Rev. 1.00 Sep. 21, 2006 Page 224 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W Description Clock Select 1, 0 Select clock source for FRC. 00: /2 internal clock source 01: /8 internal clock source 10: /32 internal clock source 11: External clock source (counting at FTCI rising edge) 11.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C. Bit 7 Bit Name ICRDMS Initial Value 0 R/W R/W Description Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0: The normal operating mode is specified for ICRD 1: The operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R/W Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read from or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0: ICRA, ICRB, and ICRC are selected 1: OCRAR, OCRAF, and OCRDM are selected Rev. 1.00 Sep. 21, 2006 Page 225 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Bit 4 Bit Name OCRS Initial Value 0 R/W R/W Description Output Compare Register Select OCRA and OCRB share the same address. The OCRS determines which register is selected when the shared address is read from or written to. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA). 0: Output compare A output is disabled 1: Output compare A output is enabled 2 OEB 0 R/W Output Enable B Enables or disables output of the output compare B output pin (FTOB). 0: Output compare B output is disabled 1: Output compare B output is enabled 1 OLVLA 0 R/W Output Level A Selects the level to be output at the output compare A output pin (FTOA) in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. 0: 0 is output at compare-match A 1: 1 is output at compare-match A 0 OLVLB 0 R/W Output Level B Selects the level to be output at the output compare B output pin (FTOB) in response to compare-match B (signal indicating a match between the FRC and OCRB values). 0: 0 is output at compare-match B 1: 1 is output at compare-match B Rev. 1.00 Sep. 21, 2006 Page 226 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.4 11.4.1 Operation Pulse Output Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.2 Example of Pulse Output Rev. 1.00 Sep. 21, 2006 Page 227 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.5 11.5.1 Operation Timing FRC Increment Timing Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (). Internal clock FRC input clock FRC N-1 N N+1 Figure 11.3 Increment Timing with Internal Clock Source External clock input pin FRC input clock FRC N N+1 Figure 11.4 Increment Timing with External Clock Source Rev. 1.00 Sep. 21, 2006 Page 228 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare output pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A. FRC N N+1 N N+1 OCRA N N Compare-match A signal Clear* OLVLA Output compare A output pin FTOA Note : * Indicates instruction execution by software. Figure 11.5 Timing of Output Compare A Output 11.5.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation. Compare-match A signal FRC N H'0000 Figure 11.6 Clearing of FRC by Compare-Match A Signal Rev. 1.00 Sep. 21, 2006 Page 229 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected. Input capture input pin Input capture signal Figure 11.7 Input Capture Input Signal Timing (Usual Case) If ICRA to ICRD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (). Figure 11.8 shows the timing for this case. Read cycle of ICRA to ICRD T1 T2 Input capture input pin Input capture signal Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read) Rev. 1.00 Sep. 21, 2006 Page 230 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 11.9 Buffered Input Capture Timing Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (). Figure 11.10 shows the timing when BUFEA = 1. Rev. 1.00 Sep. 21, 2006 Page 231 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) CPU read cycle of ICRA or ICRC T1 T2 FTIA Input capture signal Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) 11.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure 11.11 shows the timing of setting the ICFA to ICFD flag. Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting Rev. 1.00 Sep. 21, 2006 Page 232 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 11.12 shows the timing of setting the OCFA or OCFB flag. FRC N N+1 OCRA, OCRB N Compare-match signal OCFA, OCFB Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting 11.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of setting the OVF flag. Rev. 1.00 Sep. 21, 2006 Page 233 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) FRC H'FFFF H'0000 Overflow signal OVF Figure 11.13 Timing of Overflow Flag (OVF) Setting 11.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 11.14 shows the OCRA write timing. FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 11.14 OCRA Automatic Addition Timing Rev. 1.00 Sep. 21, 2006 Page 234 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 11.15 shows the timing of setting the mask signal. Figure 11.16 shows the timing of clearing the mask signal. Input capture signal Input capture mask signal Figure 11.15 Timing of Input Capture Mask Signal Setting FRC N N+1 ICRD + OCRDM x 2 N Compare-match signal Input capture mask signal Figure 11.16 Timing of Input Capture Mask Signal Clearing Rev. 1.00 Sep. 21, 2006 Page 235 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts. The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources. Table 11.2 FRT Interrupt Sources Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt Source Input capture of ICRA Input capture of ICRB Input capture of ICRC Input capture of ICRD Compare match of OCRA Compare match of OCRB Overflow of FRC Interrupt Flag ICFA ICFB ICFC ICFD OCFA OCFB OVF DTC Activation Enable Enable Disable Disable Enable Enable Disable Low Priority High Rev. 1.00 Sep. 21, 2006 Page 236 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.7 11.7.1 Usage Notes Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict. Write cycle of FRC T1 T2 Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 11.17 Conflict between FRC Write and Clear Rev. 1.00 Sep. 21, 2006 Page 237 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict. Write cycle of FRC T1 T2 Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.18 Conflict between FRC Write and Increment Rev. 1.00 Sep. 21, 2006 Page 238 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) 11.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of conflict. Write cycle of OCR T1 T2 Address OCR address Internal write signal FRC N N+1 OCR N M Write data Compare-match signal Disabled Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used) Rev. 1.00 Sep. 21, 2006 Page 239 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Old data New data Compare-match signal Disabled FRC N N+1 OCR N Automatic addition is not performed because compare-match signals are disabled. Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) 11.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may source FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 11.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also source FRC to increment. Rev. 1.00 Sep. 21, 2006 Page 240 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) Table 11.3 Switching of Internal Clock and FRC Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low No. 1 FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 CKS bit rewrite 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite 3 Switching from high to low Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite Rev. 1.00 Sep. 21, 2006 Page 241 of 658 REJ09B0310-0100 Section 11 16-Bit Free-Running Timer (FRT) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to high FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 11.7.5 Module Stop Mode Setting FRT operation can be enabled or disabled by the module stop control register. In the initial state, FRT operation is disabled. Access to FRT registers is enabled when module stop mode is cancelled. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 242 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Section 12 16-Bit Cycle Measurement Timer (TCM) This LSI has two channels on-chip 16-bit cycle measurement timers (TCM). Each TCM has a 16bit counter that provides the basis for measuring the periods of input waveforms from fans. 12.1 * * * * * Features Capable of measuring the periods of input waveforms from fans Sensed edge is selectable 16-bit compare match 16-bit resolution Selectable counter clock Any of seven internal clocks or an external clock * Four interrupt sources Counter overflow Cycle limit overflow Compare match Triggering of input capture TIM8FR1A_000020020300 Rev. 1.00 Sep. 21, 2006 Page 243 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Figure 12.1 is a block diagram of the TCM. External clock TCMCKI Internal clock /2, /8, /16, /32, /64, /128, /256 Select clock Clock TCMCNT Clear Compare match Comparator TCMMLCM Control logic Input capture Module data bus Cycle limit overflow TCMICR TCMICRF TCMCSR TCMIER TCMCR TICI TCMI TOVMI TOVI [Legend] TCMCNT: TCMMLCM: TCMICR: TCMICRF: TCMCSR: TCMIER: TCMCR: Interrupt signals TCM timer counter TCM cycle limit register TCM input capture register TCM input capture buffer register TCM status register TCM interrupt enable register TCM control register Figure 12.1 Block Diagram of the TCM Rev. 1.00 Sep. 21, 2006 Page 244 of 658 REJ09B0310-0100 Bus interface TCMCYI Overflow Internal data bus Section 12 16-Bit Cycle Measurement Timer (TCM) 12.2 Input/Output Pins Table 12.1 lists the input and output pins for the TCMs. Table 12.1 Pin Configuration Channel 0 Pin Name TCMCKI0 TCMCYI0 1 TCMCKI1 TCMCYI1 I/O Input Input Input Input Function External counter clock input External event input External counter clock input External event input 12.3 Register Descriptions The TCMs have the following registers. * * * * * * * * * * * * * * TCM timer counter_0 (TCMCNT_0) TCM cycle limit register_0 (TCMMLCM_0) TCM input capture register_0 (TCMICR_0) TCM input capture buffer register_0 (TCMICRF_0) TCM status register_0 (TCMCSR_0) TCM control register_0 (TCMCR_0) TCM interrupt enable register_0 (TCMIER_0) TCM timer counter_1 (TCMCNT_1) TCM cycle limit register_1 (TCMMLCM_1) TCM input capture register_1 (TCMICR_1) TCM input capture buffer register_1 (TCMICRF_1) TCM status register_1 (TCMCSR_1) TCM control register_1 (TCMCR_1) TCM interrupt enable register_1 (TCMIER_1) Rev. 1.00 Sep. 21, 2006 Page 245 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.3.1 TCM Timer Counter (TCMCNT) TCMCNT is a 16-bit readable/writable up-counter. The input clock is selected by the bits CKS2 to CKS0 in TCMCR. When CKS2 to CKS0 are set to B'111, the external clock is selected. In this case, the rising or falling edge is selected by CKSEG in TCMCR. When TCMCNT overflows (counting changes the value from H'FFFF to H'0000), OVF in TCMCSR is set to 1. When the CST bit in TCMCR is cleared in timer mode, TCMCR is initialized to H'0000. In speed measurement mode, TCMCNT is cleared by detection of the first edge (the edge selected with the IEDG bit in TCMCR) of the measurement period (two periods of the input waveform form one measurement period). In timer mode, TCMCNT is always writable. TCMCNT cannot be modified in speed measurement mode. TCMCNT should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMCNT is initialized to H'0000. 12.3.2 TCM Cycle Limit Register (TCMMLCM) TCMMLCM is a 16-bit readable/writable register. TCMMLCM is available as a compare match register when the TCMMDS bit in TCMCR is cleared (operation is in timer mode). TCMMLCM is available as a cycle limit register when the TCMMDS bit in TCMCR is set to 1 (operation is in speed measurement mode). In timer mode, the value in TCMMLCM is constantly compared with that in TCMCNT, when the values match, CMF in TCMCSR is set to 1. However, comparison is disabled in the second half of a cycle of writing to TCMMLCM. In speed measurement mode, a value that sets an upper limit on the measurement period (which is formed by two periods of the input waveform) can be set in TCMMLCM. When the third edge (rising or falling as selected with the IEDG bit in TCMCR) of the measurement period is detected, the value in TCMCNT is transferred to TCMICR. At this time, the values in TCMICR and TCMMLCM are compared. The MAXOVF flag in TCMCSR is set to 1 if the value in TCMICR is greater than that in TCMMLCM. TCMMLCM should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMMLCM is initialized to H'FFFF. Rev. 1.00 Sep. 21, 2006 Page 246 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.3.3 TCM Input Capture Register (TCMICR) TCMICR is a 16-bit read only register. In timer mode, the value in TCMCNT is transferred to TCMICR on the edge selected by the IEDG bit in TCMCR. At the same time, the ICPF flag in TCMCSR is set to 1. In speed measurement mode, the value in TCMCNT is transferred to TCMICR on detection of the third edge of the measurement period. At this time, the ICPF flag in TCMCSR is set to 1. TCMICR should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMICR is initialized to H'0000. 12.3.4 TCM Input Capture Buffer Register (TCMICRF) TCMICRF is a 16-bit read only register. TCMICRF can be used as TCMICR buffer register. When input capture is generated, the value in TCMICR is transferred to TCMICRF. TCMICR and TCMICRF should always be accessed in 16-bit units and cannot be accessed in 8bit units. TCMICRF is initialized to H'0000. 12.3.5 TCM Status Register (TCMCSR) TCMCSR is an 8-bit readable/writable register that controls operation of the interrupt sources. Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Timer Overflow This flag indicates that the TCMCNT has overflowed. Only 0 can be written to clear the flag. [Setting condition] Overflow of TCMCNT (change in value from H'FFFF to H'0000) [Clearing condition] Reading OVF when OVF = 1 and then writing 0 to OVF. Rev. 1.00 Sep. 21, 2006 Page 247 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Bit 6 Bit Name MAXOVF Initial Value 0 R/W Description R/(W)* Measurement Period Limit Overflow This flag indicates that the number of cycles measured in one measurement period (two periods of the input waveform form one measurement period) in speed measurement mode has exceeded the upper limit for measurement periods, as set in TCMMLCM. Only 0 can be written to clear the flag. [Setting condition] When TCMICR is greater than TCMMLCM [Clearing condition] Reading MAXOVF when MAXOVF = 1 and then writing 0 to MAXOVF 5 CMF 0 R/(W)* Compare Match Flag (only valid in timer mode) [Setting condition] When the values in TCMCNT and TCMMLCM match. Note: CMF is not set in speed measurement mode, even when the values in TCMCNT and TCMMLCM match. [Clearing condition] Reading CMF when CMF = 1 and then writing 0 to CMF 4 CKSEG 0 R/(W)* External Clock Edge Select If bits CKS2 to CKS0 in TCMCR are set to B'111, this bit selects the edge for counting of external count clock edge. 0: Count falling edges of the external clock. 1: Count rising edges of the external clock. Rev. 1.00 Sep. 21, 2006 Page 248 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Bit 3 Bit Name ICPF Initial Value 0 R/W Description R/(W)* Input Capture Generation Timer mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on generation of an input capture signal. This flag is set when the input capture signal is generated, i.e. on detection of the edge selected by the IEDGD bit on the TCMCYI input pin. Speed measurement mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on detection of the third edge (rising or falling as determined by the IEDG bit in TCMCR) during the measurement period. Only 0 can be written to clear the flag. [Setting condition] Generation of the input capture signal [Clearing condition] Reading ICPF when ICPF = 1 and then writing 0 to ICPF 2 to 0 Note: * All 0 R/W Reserved The initial value should not be changed. Only 0 can be written to clear the flag. 12.3.6 TCM Control Register (TCMCR) TCMCR is an 8-bit readable/writable register. TCMCR selects input capture input edge, counter start, and counter clock, and controls operation mode. Bit 7 Bit Name CST Initial Value 0 R/W R/W Description Counter Start In timer mode, setting this bit to 1 starts counting by TCMCNT; clearing this bit stops counting by TCMCNT. Then, the counter is initialized to H'0000, and input-capture operation stops. Clear this bit and thus return TCMCNT to H'0000 in initialization for speed measurement mode. Rev. 1.00 Sep. 21, 2006 Page 249 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Bit 6 Bit Name POCTL Initial Value 0 R/W R/W Description TCMCYI Input Polarity Reversal 0: Use the TCMCYI input directly 1: Use the inverted TCMCYI input Note: Modify this bit while CST = 0 and TCMMDS = 0 5 CPSPE 0 R/W Input Capture Stop Enable Controls whether or not counting up by TCMCNT and inputcapture operation stop or continue when MAXOVF is set to 1 in speed measurement mode. The bit does not affect operation in timer mode. 0: Counting up and input-capture operation continue when the MAXOVF flag is set to 1. 1: Counting up and input-capture operation stop when the MAXOVF flag is set to 1. 4 IEDG 0 R/W Input Edge Select In timer mode, selects the falling or rising edge of the TCMCYI input for use in input capture, in combination with the value of the POCTL bit. In speed-measurement mode, selects the falling or rising edge of the TCMCYI input for use in measurement, in combination with the value of the POCTL bit. POCTL = 0 0: Selects the rising edge of the TCMCYI input 1: Selects the falling edge of the TCMCYI input POCTL = 1 0: Selects the falling edge of the TCMCYI input 1: Selects the rising edge of the TCMCYI input 3 TCMMDS 0 R/W TCM Mode Select Selects the TCM operating mode. 0: Timer mode The TCM provides compare match and input capture facilities. 1: Speed measurement mode TCMCNT should be initialized to H'0000. Clear the CST in TCMCR to 0 before setting to speed measurement mode. Rev. 1.00 Sep. 21, 2006 Page 250 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2, 1, 0 Selects the clock signal for input to TCMCNT. Note: Modify this bit when CST = 0 and TCMMDS = 0 000: Count /2 internal clock 001: Count /8 internal clock 010: Count /16 internal clock 011: Count /32 internal clock 100: Count /64 internal clock 101: Count /128 internal clock 110: Count /256 internal clock 111: Count external clock (select the external clock edge with CKSEG in TCMCSR.) 12.3.7 TCM Interrupt Enable Register (TCMIER) TCMIER is an 8-bit readable/writable register that enables or disables interrupt requests. Bit 7 Bit Name OVIE Initial Value 0 R/W R/W Description Counter Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the OVF flag in TCMCSR to 1. 0: Disable interrupt requests by OVF 1: Enable interrupt requests by OVF 6 MAXOVIE 0 R/W Measurement Period Limit Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the MAXOVF flag in TCMCSR to 1. 0: Disable interrupt requests by MAXOVF 1: Enable interrupt requests by MAXOVF Rev. 1.00 Sep. 21, 2006 Page 251 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Bit 5 Bit Name CMIE Initial Value 0 R/W R/W Description Compare Match Interrupt Enable Enables or disables the issuing of interrupt requests when the CMF bit in TCMCSR is set to 1. 0: Disable interrupt requests by CMF 1: Enable interrupt requests by CMF 4 TCMIPE 0 R/W Input Capture Input Enable Enables input to the pin. 0: Disable input 1: Enable input Note: Modify this bit when CST = 0 and TCMMDS = 0. 3 ICPIE 0 R/W Input Capture Interrupt Enable Enables or disables interrupt requests when the ICPF flag in TCMCSR is set to 1. 0: Disable interrupt requests by ICPF 1: Enable interrupt requests by ICPF 2 1 0 0 0 0 R/W R/W R Reserved The initial value should not be changed. Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Sep. 21, 2006 Page 252 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.4 Operation TCMCNT operates in timer mode or speed measurement mode. TCMCNT is in timer mode after a reset. 12.4.1 (1) Timer Mode Counter Operation TCMCNT operates as a free running counter in timer mode. TCMCNT starts counting up when the CST bit in TCMCR is set to 1. When TCMCNT overflows (the value changes from H'FFFF to H'0000), the OVF bit in TCMCSR is set to 1 and an interrupt request is generated if the OVIE bit in TCMIER is 1. Figure 12.2 shows an example of free running counter operation. In addition, figure 12.3 shows TCMCNT count timing of external clock operation. The external clock should have a pulse width of no less than 1.5 cycles. The counter will not operate correctly if the pulses are narrower than this. /4 TCMCNT input clock TCMCNT N-1 N N+1 Figure 12.2 Example of Free Running Counter Operation External clock TCMCNT input clock TCMCNT N-1 N N+1 Figure 12.3 Count Timing of External Clock Operation (Falling Edges) Rev. 1.00 Sep. 21, 2006 Page 253 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) (2) Input Capture The value in TCMCNT is transferred to TCMICR by detecting input edge of TCMCYI pin in timer mode. At this time, the ICPF flag in TCMCSR is set. Detection of rising or falling edges is selectable. Figure 12.4 shows an example of the timing of input capture operations and figure 12.5 shows buffer operation of input capture. TCMCYI Input capture signal TCMCNT N-1 N Capture is generated N+1 N+2 TCMICR M N ICPF Figure 12.4 Input Capture Operation Timing (Sensing of Rising Edges) TCMCYI Input capture signal TCMCNT N-1 N K K+1 TCMICR M N K TCMICRF L M N Figure 12.5 Buffer Operation of Input Capture Rev. 1.00 Sep. 21, 2006 Page 254 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) (3) CMF Set Timing when a Compare Match occurs The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM match in timer mode. Therefore, a compare match signal is not generated until a further cycle of the TCMCNT input clock is generated after a match between the values in TCMCNT and TCMMLCM. Figure 12.6 shows the timing with which the CMF flag is set. TCMCNT N N+1 TCMMLC N Compare match signal CMF Figure 12.6 Timing of CMF Flag Setting on a Compare Match Rev. 1.00 Sep. 21, 2006 Page 255 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.4.2 (1) Speed Measurement Mode Counter Operation Setting the TCMMDS bit in TCMCR to 1 selects speed measurement mode, in which counting up proceeds regardless of the setting of the CST bit in TCMCR. TCMCNT is cleared to H'0000 on detection of the first edge in the measurement period and counts up from there. Figure 12.7 shows an example of counter operation in speed measurement mode. TCMCYI TCMCNT clear signal TCMCNT input clock TCMCNT N H'0000 H'0001 H'0002 H'0003 H'0000 H'0001 Figure 12.7 Example of Counter Operation in Speed Measurement Mode (2) Measuring a Speed In speed measurement mode, two cycles of the input waveform for TCM form one measurement cycle. Start by setting TCMMDS = 0 and then set CST = 0, which clears TCMCNT to H'0000. After that, set an upper limit on the measurement cycle in the TCMMLCM register. Finally, place the timer in speed measurement mode by setting the TCMMDS bit in TCMCR to 1. TCMCNT will count cycles of the selected clock. On detection of the first edge (either rising or falling as selected with the IEDG bit in TCMCR) of the measurement cycle, TCMCNT is automatically cleared to H'0000. On detection of the third edge, the value in TCMCNT is transferred to TCMICR. At this time, the value in TCMICR is compared with the value in TCMMLCM. If TCMICR is larger than TCMMLCM, the MAXOVF bit in TCMCSR is set to 1. If generation of the corresponding interrupt request is enabled by the setting in TCMIER, the request is generated. In addition, on detection of the third edge, TCMCNT is cleared to H'0000, and the next round of measurement starts. When the CPSPE bit in TCMCR has been cleared to 0, the next round of speed measurement will start, even if the MAXOVF flag is set to 1. Rev. 1.00 Sep. 21, 2006 Page 256 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) If the MAXOVF flag is set to 1 while the CPSPE bit in TCMCR is set to 1, counting up by TCMCNT stops and so does speed measurement. Subsequently clearing MAXOVF to 0 automatically clears TCMCNT to H'0000, and counting up for speed measurement is then restarted. Figure 12.8 shows an example of timing in speed measurement. Measurement cycle (TR) TCMCYI Input capture signal TCMCNT TCMCNT cleared at first rising edge TCMCNT cleared at third rising edge H'0000 D H'0000 Capture generated TCMICR A D MAXOVF When TCMICR > TCMMLCM A TCMICRF Figure 12.8 Example of Timing in Speed Measurement (3) Determination of Fan Stoppage Either of two sets of conditions can be considered to represent fan-stopped states. The fan can be considered to have stopped when a timer overflow is generated within the period from the start of speed measurement mode to detection of the first edge (rising or falling as selected with the IEDG bit in TCMCR). Figure 12.9 shows an example of the timing of fan-stopped state (1). Rev. 1.00 Sep. 21, 2006 Page 257 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) TCMCYI Start of first measurement TCMMDS TCMCNT H'0000 H'FFFF H'0000 H'0001 H'0000 OVF Determined as fan-stopped state MAXOVF MAXOVF flag is not set because the first cycle measurement is not started Figure 12.9 Example of Timing in Fan-Stopped State (1) Speed measurement stops if MAXOVF is set to 1 while the CPSPE bit in TCMCR is set to 1. Subsequently clearing MAXOVF to 0 restarts speed measurement. In this case, the fan can be considered to have stopped if a timer overflow is generated before detection of the first edge. Figure 12.10 shows an example of the timing of the fan-stopped state (2). TCMCYI Start of first measurement CPSPE TCMCNT H'5555 H'0000 H'FFFF H'0000 H'0001 H'0000 OVF Determined as fan-stopped state MAXOVF Restart of measurement MAXOVF flag is not set because the first cycle measurement is not started Figure 12.10 Example of Timing in Fan-Stopped State (2) Rev. 1.00 Sep. 21, 2006 Page 258 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) (4) Example of Settings for Speed Measurement Mode Figure 12.11 shows an example of the flow when speed measurement mode is to be used. Start [1] Set timer mode. Initialization [2] Stop TCMCNT and initialize to H'0000. [3] Set an upper limit on the measurement period. Set TCMMDS to 0 [1] [4] Enable interrupts. [5] Set speed measurement mode to start speed measurement. [6] Processing for the fan-stopped state. Set TCMMLCM [3] [7] Processing for the cycle upper limit over. Set OVIE and MAXOVIE to 1 [4] [8] Speed measurement is completed. Set CST (TCMCR) to 0 [2] Set TCMMDS to 1 [5] OVF = 1? or MAXOVF = 1? No Set TCMMDS to 0 Yes Interrupt is generated [8] Yes MAXOVF = 1? No Processing for fan-stopped state [6] Processing for cycle upper limit over [7] End of measurement End of exception handling Figure 12.11 Example of Speed Measurement Mode Settings Rev. 1.00 Sep. 21, 2006 Page 259 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) (5) Formula for Calculating Fan Speed from Results in Speed Measurement Mode Two cycles of the input waveform from a fan form a single measurement cycle in speed measurement mode. The rotation speed of a fan is given by the following formula. * When the fan motor generates two pulses per rotation: Fan rotation speed (RPM) = TCMCNT input clock frequency x 60 x 2 Number of captures counted by TCMCNT (6) Measurement Error and Range in Speed Measurement Mode When the TCM is used in speed measurement mode, take the range of error in measurement and the range of measurable frequencies into account in selecting the source clock to drive counting. When measuring the pulses of a signal input via the TCMCYI pin, the possible error in the number counted due to the conditions of measurement is N 1 (N: the correct number of input TCM cycles). Therefore, the error in measurement is given by the following formula. Measurement error = N1 N x 100% - 1 = 1 N x 100% Table 12.2 lists the ranges of error in measurement when the TCM period is from 60 to 3.75 ms and the frequency of the system clock is from 8 to 20 MHz. Table 12.2 Range of Error in Measurement Input Clock Frequency of TCMCNT Number Counted by TCMCNT /2 /8 /16 /32 /64 /128 /256 15000 to 65535 3750 to 65535 1875 to 65535 9371 to 65535 4681 to 37500 2341 to 18750 1171 to 9375 H'3A98 to H'FFFF H'EA6 to H'FFFF H'753 to H'FFFF H'3A91 to H'FFFF H'1D41 to H'927C H'EA1 to H'493E H'751 to H'249F Range of Error (%) 0.001 to 0.006 0.001 to 0.002 0.001 to 0.05 0.001 to 0.11 0.002 to 0.21 0.005 to 0.43 0.01 to 0.85 Rev. 1.00 Sep. 21, 2006 Page 260 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) Table 12.3 lists the measurable ranges of frequency for an error of measurement of 5% or less when the frequency of the system clock is 8, 10, or 20 MHz. Table 12.3 Range of Measurement Speed Input Clock Frequency of TCMCNT /2 8 MHz 10 MHz 20 MHz /8 8 MHz 10 MHz 20 MHz /16 8 MHz 10 MHz 20 MHz /32 8 MHz 10 MHz 20 MHz /64 8 MHz 10 MHz 20 MHz /128 8 MHz 10 MHz 20 MHz /256 8 MHz 10 MHz 20 MHz Number Counted by TCMCNT 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 20 to 65535 Measurable Range (RMP) 24000000 to 7324 30000000 to 9155 60000000 to 18310 6000000 to 1830 7500000 to 2288 15000000 to 4576 3000000 to 914 3750000 to 1144 7500000 to 2288 1500000 to 456 1875000 to 572 3750000 to 1144 750000 to 228 937500 to 286 1875000 to 572 375000 to 114 468750 to 143 937500 to 286 187500 to 56 234375 to 71 468750 to 143 Rev. 1.00 Sep. 21, 2006 Page 261 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.5 Interrupt Sources TCM has four interrupt sources: TICI, TCMI, TOVMI, and TOVI. Each interrupt source is either enabled or disabled by the corresponding interrupt enable bit in TCMIER and independently transferred to the interrupt controller. Table 12.4 lists the interrupt sources in priority order. TICI and TCMI interrupts can be set up as activation sources for the on-chip DTC. Table 12.4 TCM Interrupt Sources Channel TCM_0 Name TICI0 TCMI0 Interrupt Source TCMICR_0 input capture Interrupt Flag ICPF_0 DTC Activation Available Available Not available Not available Available Available Not available Not available Low Priority High TCMMLCM_0 compare CMF_0 match TOVMI0 TCMMLCM_0 overflow MAXOVF_0 TOVI0 TCM_1 TICI1 TCMI1 TCMCNT_0 overflow TCMICR_1 input capture OVF_0 ICPF_1 TCMMLCM_1 compare CMF_1 match TOVMI1 TCMMLCM_1 overflow MAXOVF_1 TOVI1 TCMCNT_1 overflow OVF_1 Rev. 1.00 Sep. 21, 2006 Page 262 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.6 12.6.1 Usage Notes Conflict between TCMCNT Write and Count-Up Operation When a conflict between TCMCNT write and count-up operation occurs in the second half of the TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority. Figure 12.12 shows the timing of this conflict. T1 T2 Internal write signal Internal clock TCMCNT input clock TCMCNT N M M+1 Figure 12.12 Conflict between TCMCNT Write and Count-Up Operation 12.6.2 Conflict between TCMMLCM Write and Compare Match When a conflict between TCMMLCM write and a compare match should occur in the second half of a cycle of writing to TCMMLCM, writing to TCMMLCM takes priority and the compare match signal is inhibited. Figure 12.13 shows the timing of this conflict. T1 T2 Internal write signal TCMCNT N N+1 TCMMLCM N M Compare match signal Inhibited Figure 12.13 Conflict between TCMMLCM Write and Compare Match Rev. 1.00 Sep. 21, 2006 Page 263 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.6.3 Conflict between TCMICR Read and Input Capture When operation is in timer mode and the corresponding input capture signal is detected during reading of TCMICR, the input capture signal is delayed by one system clock (). Figure 12.14 shows the timing of this conflict. TCMCYI TCMICR read signal Input capture signal TCMCNT N-1 N Capture genearted N+1 N+2 TCMICR M N ICPF Figure 12.14 Conflict between TCMICR Read and Input Capture Rev. 1.00 Sep. 21, 2006 Page 264 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.6.4 Conflict between Edge Detection in Speed Measurement Mode and Writing to TCMMLCM If the selected edge of TCMCYI is detected in the second half of a cycle of writing to the register (TCMMLCM) in speed measurement mode, the detected edge signal is delayed by one cycle of the system clock (). Figure 12.15 shows the timing of this conflict. TCMCYI Input capture signal Internal write signal TCMCNT A Capture generated at the third rising edge of measurement cycle Capture generated H'0000 TCMICR A MAXOVF TCMICR > TCMMLCM (Upper limit over) Figure 12.15 Conflict between Edge Detection and Register Write (Speed Measurement Mode) Rev. 1.00 Sep. 21, 2006 Page 265 of 658 REJ09B0310-0100 Section 12 16-Bit Cycle Measurement Timer (TCM) 12.6.5 Conflict between Edge Detection in Speed Measurement Mode and Clearing of TCMMDS Bit in TCMCR If the CST bit in TCMCR is set to 1 in speed measurement mode, and the TCMMDS bit in TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of the selected edge will cause the timer to continue to operate in speed measurement mode. The timer will not make the transition to timer mode until the next detection of the selected edge. Thus, ensure that the CST bit is cleared to 0 in speed measurement mode. Figure 12.16 shows the timing of this conflict. TCMCYI Input capture signal WRTCMCR TCMCNT cleared at the first rising edge Capture of input capture generated TCMCNT not cleared TCMMDS Capture generated in speed measurement mode TCMCNT A H'0000 B B+1 TCMICR A B Figure 12.16 Conflict between Edge Detection and Clearing of TCMMDS (to Switch from Speed Measurement Mode to Timer Mode) 12.6.6 Setting for Module Stop Mode The module-stop control register can be used to select either continuation or stoppage of TCM operation in module-stopped mode. The default setting is for TCM operation to stop. TCM registers become accessible on release from module-stopped mode. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 266 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.1 Features * Selection of clock sources The counter input clock can be selected from six internal clocks and an external clock * Selection of three ways to clear the counters The counters can be cleared on compare-match A, compare-match B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. * Cascading of two channels Cascading of TMR_0 and TMR_1 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). Cascading of TMR_Y and TMR_X Operation as a 16-bit timer can be performed using TMR_Y as the upper half and TMR_X as the lower half (16-bit count mode). TMR_X can be used to count TMR_Y compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, compare-match B, and overflow TMR_X: Four types of interrupts: Compare-match A, compare match B, overflow, and input capture TIMH265A_000020020800 Rev. 1.00 Sep. 21, 2006 Page 267 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Figures 13.1 and 13.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X. External clock sources TMCI0 TMCI1 Internal clock sources TMR_0 /2, /8, /32, /64, /256, /1024 TMR_1 /2, /8, /64, /128, /1024, /2048 Clock 1 Clock 0 Clock select TCORA_0 Compare-match A1 Compare-match A0 Comparator A_0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B_0 TMO1 TMRI1 Control logic TCORB_0 TCORB_1 Comparator B_1 TCORA_1 Comparator A_1 TMO0 TMRI0 TCNT_0 TCNT_1 TCSR_0 TCSR_1 TCR_0 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 [Legend] TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0: TCR_1 Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0 TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1: Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1 Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) Rev. 1.00 Sep. 21, 2006 Page 268 of 658 REJ09B0310-0100 Internal bus Section 13 8-Bit Timer (TMR) External clock sources TMCIY TMCIX Internal clock sources TMR_X , /2, /4, /2048, /4096, /8192 TMR_Y /4, /256, /2048, /4096, /8192, /16384 Clock select Clock X Clock Y TCORA_Y Compare-match AX Compare-match AY Overflow X Overflow Y Clear Y Clear X TCORA_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X Compare- match BX TMOY TMRIY Compare-match BY Comparator B_Y Comparator B_X Control logic TMOX TMRIX Input capture TICRR TICRF TICR Compare-match C Comparator C + TCORC TCSR_Y TCR_Y TCSR_X TCR_X Interrupt signals CMIAY CMIBY OVIY ICIX [Legend] TCORA_Y: TCORB_Y: TCNT_Y: TCSR_Y: TCR_Y: Time constant register A_Y Time constant register B_Y Timer counter_Y Timer control/status register_Y Timer control register_Y TCORA_X: TCORB_X: TCNT_X: TCSR_X: TCR_X: TICR: TCORC: TICRR: TICRF: Time constant register A_X Time constant register B_X Timer counter_X Timer control/status register_X Timer control register_X Input capture register Time constant register C Input capture register R Input capture register F Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) Rev. 1.00 Sep. 21, 2006 Page 269 of 658 REJ09B0310-0100 Internal bus TCORB_Y TCORB_X Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration Channel TMR_0 Name Timer output Timer clock input Timer reset input TMR_1 Timer output Timer clock input Timer reset input TMR_Y Timer clock/reset input Timer output TMR_X Timer output Timer clock/reset input Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Output controlled by compare-match External clock input for the counter External reset input for the counter Output controlled by compare match External clock input for the counter External reset input for the counter External clock input/external reset input for the counter Output controlled by compare-match Output controlled by compare-match External clock input/external reset input for the counter TMIY Input (TMCIY/TMRIY) TMOY TMOX Output Output TMIX Input (TMCIX/TMRIX) Rev. 1.00 Sep. 21, 2006 Page 270 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). TMR_0 * Timer counter_0 (TCNT_0) * Time constant register A_0 (TCORA_0) * Time constant register B_0 (TCORB_0) * Timer control register_0 (TCR_0) * Timer control/status register_0 (TCSR_0) TMR_1 * Timer counter_1 (TCNT_1) * Time constant register A_1 (TCORA_1) * Time constant register B_1 (TCORB_1) * Timer control register_1 (TCR_1) * Timer control/status register_1 (TCSR_1) TMR_Y * Timer counter_Y (TCNT_Y) * Time constant register A_Y (TCORA_Y) * Time constant register B_Y (TCORB_Y) * Timer control register_Y (TCR_Y) * Timer control/status register_Y (TCSR_Y) * Timer connection register S (TCONRS) TMR_X * Timer counter_X (TCNT_X) * Time constant register A_X (TCORA_X) * Time constant register B_X (TCORB_X) * Timer control register_X (TCR_X) * Timer control/status register_X (TCSR_X) * Input capture register (TICR) * Time constant register (TCORC) * Input capture register R (TICRR) * Input capture register F (TICRF) Rev. 1.00 Sep. 21, 2006 Page 271 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) * Timer connection register I (TCONRI) For both TMR_Y and TMR_X * Timer XY control register (TCRXY) Note: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be switched by the TMRX/Y bit in TCONRS. TCNT_Y, TCORA_Y, TCORB_Y, and TCR_Y can be accessed when the TMRX/Y bit in TCONRS is set to 1. TCNT_X, TCORA_X, TCORB_X, and TCR_X can be accessed when the TMRX/Y bit in TCONRS are cleared to 0. 13.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_X and TCNT_Y) comprise a single 16-bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-match A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. 13.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_X and TCORA_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 13.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_X and TCORB_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. Rev. 1.00 Sep. 21, 2006 Page 272 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1, 0 These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and count condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 13.2. Rev. 1.00 Sep. 21, 2006 Page 273 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Table 13.2 Clock Input to TCNT and Count Condition (1) TCR Channel CKS2 TMR_0 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 STCR ICKS1 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- ICKS0 -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0* Rev. 1.00 Sep. 21, 2006 Page 274 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) TCR Channel CKS2 Common 1 1 1 Note: * CKS1 0 1 1 CKS0 1 0 1 STCR ICKS1 -- -- -- ICKS0 -- -- -- Description Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made. Table 13.2 Clock Input to TCNT and Count Condition (2) TCR Channel CKS2 TMR_Y 0 0 0 0 1 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 TCRXY CKSX -- -- -- -- -- -- -- -- -- -- -- -- -- CKSY 0 0 0 0 0 1 1 1 1 1 x x x Description Disables clock input Increments at /4 Increments at /256 Increments at /2048 Disables clock input Disables clock input Increments at /4096 Increments at /8192 Increments at /16384 Increments at overflow signal from TCNT_X* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock Rev. 1.00 Sep. 21, 2006 Page 275 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) TCR Channel CKS2 TMR_X 0 0 0 0 1 0 0 0 0 1 1 1 1 Note: * CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 TCRXY CKSX 0 0 0 0 0 1 1 1 1 1 x x x CKSY -- -- -- -- -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at Increments at /2 Increments at /4 Disables clock input Disables clock input Increments at /2048 Increments at /4096 Increments at /8192 Increments at compare-match A from TCNT_Y* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made. [Legend] x: Don't care : Invalid Rev. 1.00 Sep. 21, 2006 Page 276 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. * TCSR_0 Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_0 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ADTE 0 R/W A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled Rev. 1.00 Sep. 21, 2006 Page 277 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Bit 3 2 Bit Name OS3 OS2 Initial Value 0 0 R/W R/W R/W Description Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. * TCSR_1 Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA Rev. 1.00 Sep. 21, 2006 Page 278 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Bit 5 Bit Name OVF Initial Value 0 R/W Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 3 2 -- OS3 OS2 1 0 0 R R/W R/W Reserved This bit is always read as 1 and cannot be modified. Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. * TCSR_X Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB Rev. 1.00 Sep. 21, 2006 Page 279 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Bit 6 Bit Name CMFA Initial Value 0 R/W Description R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICF 0 R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order. [Clearing condition] Read ICF when ICF = 1, then write 0 in ICF 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMOX pin output level is to be changed by compare-match B of TCORB_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. Rev. 1.00 Sep. 21, 2006 Page 280 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) * TCSR_Y Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICIE 0 R/W Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1. 0: ICF interrupt request (ICIX) is disabled 1: ICF interrupt request (ICIX) is enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMOY pin output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Rev. 1.00 Sep. 21, 2006 Page 281 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Bit 1 0 Bit Name OS1 OS0 Initial Value 0 0 R/W R/W R/W Description Output Select 1, 0 These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. 13.3.6 Time Constant Register C (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. 13.3.7 Input Capture Registers R and F (TICRR and TICRF) TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI is set to 1, the contents of TCNT are transferred at the rising edge and falling edge of the external reset input (TMRIX) in that order. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are initialized to H'00. Rev. 1.00 Sep. 21, 2006 Page 282 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.3.8 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Bit Bit Name Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. 4 ICST Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX [Setting condition] When 1 is written in ICST after reading ICST = 0 3 to 0 -- All 0 R/W Reserved The initial values should not be modified. 7 to 5 -- 13.3.9 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Bit 7 Bit Name TMRX/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 13.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 6 to 0 All 0 R/W Reserved The initial values should not be modified. Rev. 1.00 Sep. 21, 2006 Page 283 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Table 13.3 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 0 1 TMR_X TCR_X TMR_Y TCR_Y H'FFF1 TMR_X TMR_Y H'FFF2 TMR_X TMR_Y H'FFF3 TMR_X TICRF TMR_Y H'FFF4 TMR_X TCNT TMR_Y H'FFF5 TMR_X TCORC TMR_Y H'FFF6 TMR_X H'FFF7 TMR_X TCSR_X TICRR TCORA_X TCORB_X TCSR_Y TCORA_Y TCORB_Y TCNT_Y 13.3.10 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock. Bit 7, 6 5 4 3 to 0 Initial Bit Name Value CKSX CKSY -- All 0 0 0 All 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. TMR_X Clock Select For details about selection, see table 13.2. TMR_Y Clock Select For details about selection, see table 13.2. Reserved The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 284 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.4 13.4.1 Operation Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 13.3 Pulse Output Example Rev. 1.00 Sep. 21, 2006 Page 285 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.5 13.5.1 Operation Timing TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks () for a single edge and at least 2.5 system clocks () for both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock TCNT input clock TCNT N-1 N N+1 Figure 13.4 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 13.5 Count Timing for External Clock Input (Both Edges) Rev. 1.00 Sep. 21, 2006 Page 286 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 13.6 shows the timing of CMF flag setting. TCNT N N+1 TCOR Compare-match signal N CMF Figure 13.6 Timing of CMF Setting at Compare-Match 13.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 13.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. Compare-match A signal Timer output pin Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal Rev. 1.00 Sep. 21, 2006 Page 287 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match. Compare-match signal TCNT N H'00 Figure 13.8 Timing of Counter Clear by Compare-Match 13.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 13.9 shows the timing of clearing the counter by an external reset input. External reset input pin Clear signal TCNT N-1 N H'00 Figure 13.9 Timing of Counter Clear by External Reset Input Rev. 1.00 Sep. 21, 2006 Page 288 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. TCNT H'FF H'00 Overflow signal OVF Figure 13.10 Timing of OVF Flag Setting Rev. 1.00 Sep. 21, 2006 Page 289 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 13.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits. (1) Setting of compare-match flags * The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. (2) Counter clear specification * If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. (3) Pin output * Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. * Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 13.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each or TMR_0 and TMR_1. Rev. 1.00 Sep. 21, 2006 Page 290 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 13.7.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X occupying the lower 8 bits. (1) Setting of compare-match flags * The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs. * The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs. (2) Counter clear specification * If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at compare-match, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y are also cleared when counter clear by the TMRIY pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of TCNT_X can be cleared by the counter. (3) Pin output * Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance with the upper 8-bit compare-match conditions. * Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance with the lower 8-bit compare-match conditions. 13.7.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1, TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Rev. 1.00 Sep. 21, 2006 Page 291 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. (1) Input Capture Signal Input Timing Figure 13.11 shows the timing of the input capture operation. TMRIX Input capture signal TCNT_X TICRR TICRF M m n n n+1 n m N N N+1 Figure 13.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock () cycle. Figure 13.12 shows the timing of this operation. Rev. 1.00 Sep. 21, 2006 Page 292 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) TICRR, TICRF read cycle T1 T2 TMRIX Input capture signal Figure 13.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) (2) Selection of Input Capture Signal Input TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 13.4. Table 13.4 Input Capture Signal Selection TCONRI Bit 4 ICST 0 1 Description Input capture function not used TMIX pin input selection Rev. 1.00 Sep. 21, 2006 Page 293 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.5 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 13.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X Channel TMR_0 Name CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY TMR_X ICIX CMIAX CMIBX OVIX Interrupt Source TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Input capture TCORA_X compare-match TCORB_X compare-match TCNT_X overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF ICF CMFA CMFB OVF Low Interrupt Priority High Rev. 1.00 Sep. 21, 2006 Page 294 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.9 13.9.1 Usage Notes Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 13.13, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.13 Conflict between TCNT Write and Clear Rev. 1.00 Sep. 21, 2006 Page 295 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.9.2 Conflict between TCNT Write and Count-Up If a count-up occurs during the T2 state of a TCNT write cycle as shown in figure 13.14, the counter write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.14 Conflict between TCNT Write and Count-Up Rev. 1.00 Sep. 21, 2006 Page 296 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Disabled Figure 13.15 Conflict between TCOR Write and Compare-Match Rev. 1.00 Sep. 21, 2006 Page 297 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) 13.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the operation follows the output status that is defined for compare-match A or B, according to the priority of the timer output shown in table 13.6. Table 13.6 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 13.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.7 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 13.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks. Rev. 1.00 Sep. 21, 2006 Page 298 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) Table 13.7 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low 1 to low level* No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit rewrite N+1 2 Clock switching from low to high level*2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite 3 Clock switching from high to low level*3 Clock before switchover Clock after switchover TCNT clock *4 TCNT N N+1 CKS bit rewrite N+2 Rev. 1.00 Sep. 21, 2006 Page 299 of 658 REJ09B0310-0100 Section 13 8-Bit Timer (TMR) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to high level TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 13.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 13.9.7 Module Stop Mode Setting TMR operation can be enabled or disabled using the module stop control register. The initial setting is for TMR operation to be halted. Register access is enabled by canceling the module stop mode. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 300 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer is an 8-bit timer that can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 are shown in figure 14.1. 14.1 Features * Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, an internal reset or an internal NMI interrupt is generated. Internal Timer Mode: * If the counter overflows, an internal timer interrupt (WOVI) is generated. WDT0102A_000020020300 Rev. 1.00 Sep. 21, 2006 Page 301 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock selection /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock TCNT_0 TCSR_0 Module bus WDT_0 Bus interface WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) Interrupt control Reset control Overflow Clock Clock selection /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock Internal reset signal*1 SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 TCNT_1 TCSR_1 Module bus WDT_1 [Legend] TCSR_0: Timer control/status register_0 TCNT_0: Timer counter_0 TCSR_1: Timer control/status register_1 TCNT_1: Timer counter_1 Bus interface Notes: 1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1. Figure 14.1 Block Diagram of WDT Rev. 1.00 Sep. 21, 2006 Page 302 of 658 REJ09B0310-0100 Internal bus Internal bus Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name Symbol I/O Input Function Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input EXCL pin 14.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 14.6.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). * Timer counter (TCNT) * Timer control/status register (TCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 303 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0 Bit 7 Initial Bit Name Value OVF 0 R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * When TCSR is read when OVF = 1, then 0 is written to OVF When 0 is written to TME 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 3 0 R/W R/W Reserved The initial value should not be changed. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested RST/NMI 0 Rev. 1.00 Sep. 21, 2006 Page 304 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) Bit 2 1 0 Initial Bit Name Value CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: /2 (frequency: 25.6 s) 001: /64 (frequency: 819.2 s) 010: /128 (frequency: 1.6 ms) 011: /512 (frequency: 6.6 ms) 100: /2048 (frequency: 26.2 ms) 101: /8192 (frequency: 104.9 ms) 110: /32768 (frequency: 419.4 ms) 111: /131072 (frequency: 1.68 s) Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 21, 2006 Page 305 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) * TCSR_1 Bit 7 Initial Bit Name Value OVF 0 R/W 1 Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * When TCSR is read when OVF = 1* , then 0 is written to OVF When 0 is written to TME 2 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested Rev. 1.00 Sep. 21, 2006 Page 306 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) Bit 2 1 0 Initial Bit Name Value CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for = 20 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (frequency: 25.6 s) 001: /64 (frequency: 819.2 s) 010: /128 (frequency: 1.6 ms) 011: /512 (frequency: 6.6 ms) 100: /2048 (frequency: 26.2 ms) 101: /8192 (frequency: 104.9 ms) 110: /32768 (frequency: 419.4 ms) 111: /131072 (frequency: 1.68 s) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: SUB/256 (cycle: 2 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 1.00 Sep. 21, 2006 Page 307 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.4 14.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks as shown in figure 14.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. Rev. 1.00 Sep. 21, 2006 Page 308 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Internal reset signal 518 System clocks WT/IT: TME: OVF: Timer mode select bit Timer enable bit Overflow flag Time Write H'00 to TCNT OVF = 1* WT/IT = 1 Write H'00 to TME = 1 TCNT Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation Rev. 1.00 Sep. 21, 2006 Page 309 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF flag of TCSR is set to 1. The timing is shown figure 14.4. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time WOVI : Interval timer interrupt request occurrence Figure 14.3 Interval Timer Mode Operation TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 14.4 OVF Flag Set Timing Rev. 1.00 Sep. 21, 2006 Page 310 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 14.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Disable Rev. 1.00 Sep. 21, 2006 Page 311 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.6 14.6.1 Usage Notes Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. (1) Writing to TCNT and TCSR (Example of WDT_0) These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.5 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the higher bytes must contain the value H'A5 and the lower bytes must contain the write data. Figure 14.5 Writing to TCNT and TCSR (WDT_0) (2) Reading from TCNT and TCSR (Example of WDT_0) These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. Rev. 1.00 Sep. 21, 2006 Page 312 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.6 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.6 Conflict between TCNT Write and Increment Rev. 1.00 Sep. 21, 2006 Page 313 of 658 REJ09B0310-0100 Section 14 Watchdog Timer (WDT) 14.6.3 Changing Values of CKS2 to CKS0 Bits If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits. 14.6.4 Changing Value of PSS Bit If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of PSS bit. 14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 1.00 Sep. 21, 2006 Page 314 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. 15.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * The on-chip baud rate generator allows any bit rate to be selected An external clock can be selected as a transfer clock source. * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources -- transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC. Asynchronous Mode: * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCI0022B_000020020700 Rev. 1.00 Sep. 21, 2006 Page 315 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors * Serial data communication with other LSIs that have the clock synchronized communication function A block diagram of the SCI is shown in figure 15.1. Module data bus RDR TDR SCMR SSR SCR BRR Baud rate generator /4 /16 /64 Clock External clock TEI TXI RXI ERI RxD RSR TSR SMR Transmission/ reception control TxD Parity check SCK Parity generation [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register Figure 15.1 Block Diagram of SCI Rev. 1.00 Sep. 21, 2006 Page 316 of 658 REJ09B0310-0100 Internal data bus Bus interface Section 15 Serial Communication Interface (SCI) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration Channel 0 Symbol* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 Note: * Input/Output Input/Output Input Output Input/Output Input Output Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 15.3 Register Descriptions The SCI has the following registers for each channel. * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit data register (TDR) Transmit shift register (TSR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Serial interface mode register (SCMR) Bit rate register (BRR) Rev. 1.00 Sep. 21, 2006 Page 317 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 1.00 Sep. 21, 2006 Page 318 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select clock source for the on-chip baud rate generator. SMR can always be read from by the CPU. Writing to SMR by the CPU is enabled only in the initial setting, and not enabled during the receive, transmit, or transfer operation. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. Rev. 1.00 Sep. 21, 2006 Page 319 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1,0 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR. 15.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. SCR can always be read from by the CPU. Writing to SCR by the CPU is enabled only in the initial setting, and not enabled during the receive, transmit, or transfer operation. For details on interrupt requests, refer to section 15.7, Interrupt Sources. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. Rev. 1.00 Sep. 21, 2006 Page 320 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Bit 5 4 3 Bit Name TE RE MPIE Initial Value 0 0 0 R/W R/W R/W R/W Description Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 15.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) [Legend] X: Don't care Rev. 1.00 Sep. 21, 2006 Page 321 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing the DTC to write data to TDR [Clearing conditions] * * 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing the DTC to read data from RDR [Clearing conditions] * * The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] * * When the next data is received while RDRF = 1 When 0 is written to ORER after reading ORER = 1 [Clearing condition] Rev. 1.00 Sep. 21, 2006 Page 322 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Bit 4 Bit Name FER Initial Value 0 R/W Description R/(W)* Framing Error [Setting condition] * * When the stop bit is 0 When 0 is written to FER after reading FER = 1 [Clearing condition] In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition] 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing the DTC to write data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 21, 2006 Page 323 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. SCMR can always be read from by the CPU. Writing to SCMR by the CPU is enabled only in the initial setting, and not enabled during the receive, transmit, or transfer operation. Bit 7 to 4 3 Bit Name -- SDIR Initial Value All 1 0 R/W R R/W Description Reserved These bits are always read as 1 and cannot be modified. Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 -- SMIF 1 0 R R/W Reserved This bit is always read as 1 and cannot be modified. Serial Communication Interface Mode Select: 0: Normal asynchronous or clocked synchronous mode 1: Reserved mode Rev. 1.00 Sep. 21, 2006 Page 324 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode. The initial value of BRR is H'FF. BRR can always be read from by the CPU. Writing to BRR by the CPU is enabled only in the initial setting, and not enabled during the receive, transmit, or transfer operation. Table 15.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode B= 64 x 2 Bit Rate x 106 2n-1 Error Error (%) = { x 106 B x 64 x 2 2n-1 x (N+1) x (N+1) - 1 } x 100 Clocked synchronous mode B= 8x2 x 106 2n-1 -- x (N+1) [Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock input. Rev. 1.00 Sep. 21, 2006 Page 325 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) 8 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 [Legend] --: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Rev. 1.00 Sep. 21, 2006 Page 326 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Operating Frequency (MHz) 12.288 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 [Legend] --: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Rev. 1.00 Sep. 21, 2006 Page 327 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Operating Frequency (MHz) 17.2032 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 16 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 166 233 166 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 [Legend] --: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Rev. 1.00 Sep. 21, 2006 Page 328 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Rev. 1.00 Sep. 21, 2006 Page 329 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M [Legend] Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* 8 N n 10 N n 16 N n 20 N Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 8 10 12 14 External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 (MHz) 16 18 20 External Input Clock (MHz) 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 2666666.7 3000000.0 3333333.3 Rev. 1.00 Sep. 21, 2006 Page 330 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 1.00 Sep. 21, 2006 Page 331 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4.1 Data Transfer Format Table 15.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 15.5, Multiprocessor Communication Function. Table 15.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 1.00 Sep. 21, 2006 Page 332 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 15.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = } (0.5 - M: N: D: L: F: 1 2N )- D - 0.5 (1 + F) - (L - 0.5) F } x 100 N [%] ... Formula (1) Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875 % However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Sep. 21, 2006 Page 333 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev. 1.00 Sep. 21, 2006 Page 334 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When an external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. Set the data transfer/receive format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] [2] [3] Set data transfer/receive format in SMR and SCMR Set value in BRR Wait [2] [4] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Figure 15.5 Sample SCI Initialization Flowchart Rev. 1.00 Sep. 21, 2006 Page 335 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Sep. 21, 2006 Page 336 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] Read TDRE flag in SSR [2] [2] No TDRE = 1 [3] Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR [4] No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. [4] Note: The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of transmission. This does not apply to the processing at step [5]. Clear TE bit in SCR to 0 [5] End of transmission Figure 15.7 Sample Serial Transmission Flowchart Rev. 1.00 Sep. 21, 2006 Page 337 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 15.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Sep. 21, 2006 Page 338 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Table 15.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flow chart for serial data reception. Table 15.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev. 1.00 Sep. 21, 2006 Page 339 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) No No SCI initialization: The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, Read ORER, PER, and PER, and FER flags in SSR to identify the [2] FER flags in SSR error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception Yes cannot be resumed if any of these flags are PER FER ORER = 1 [3] set to 1. In the case of a framing error, a break can be detected by reading the value No Error processing of the input port corresponding to the RxD (Continued on next page) pin. [4] SCI status check and receive data read: [4] Read RDRF flag in SSR Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag RDRF = 1 from 0 to 1 can also be identified by an RXI interrupt. Yes [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the Read receive data in RDR, and RDRF flag, read RDR, and clear the RDRF clear RDRF flag in SSR to 0 flag to 0. However, the RDRF flag is cleared automatically when the DTC is initiated by an All data received? [5] RXI interrupt and reads data from RDR. Initialization [1] Yes Clear RE bit in SCR to 0 End of reception [6] [Legend] : Logical OR Note: The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of reception. This does not apply to the processing at step [6]. [1] Figure 15.9 Sample Serial Reception Flowchart (1) Rev. 1.00 Sep. 21, 2006 Page 340 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 [6] No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 End Figure 15.9 Sample Serial Reception Flowchart (2) Rev. 1.00 Sep. 21, 2006 Page 341 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 1.00 Sep. 21, 2006 Page 342 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 1.00 Sep. 21, 2006 Page 343 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] Read TDRE flag in SSR [2] [2] No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR [3] Clear TDRE flag to 0 No All data transmitted? Yes [3] Read TEND flag in SSR [4] No TEND = 1 Yes No Break output? Yes [4] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Note: The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of transmission. This does not apply to the processing at step [5]. Clear TE bit in SCR to 0 [5] End of transmission Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 1.00 Sep. 21, 2006 Page 344 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data 2 MPIE bit set to 1 again (b) Data matches station's ID Figure 15.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 1.00 Sep. 21, 2006 Page 345 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Initialization Start reception [1] [1] [2] [2] [3] Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes [3] [4] [5] Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes SCI initialization: The RxD pin is automatically designated as the receive data input pin. ID reception cycle: Set the MPIE bit in SCR to 1. SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. FER ORER = 1 No Read RDRF flag in SSR [Legend] : Logical OR [4] No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 End of reception Note: The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of reception. This does not apply to the processing at step [6]. [5] Error processing (Continued on next page) [6] Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 1.00 Sep. 21, 2006 Page 346 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 [6] Clear ORER, PER, and FER flags in SSR to 0 End Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.00 Sep. 21, 2006 Page 347 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling fullduplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer/reception Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 15.14 Data Format in Clocked Synchronous Communication (LSB-First) 15.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 1.00 Sep. 21, 2006 Page 348 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR. Start initialization [1] Clear TE and RE bits in SCR to 0 [2] [3] Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] [4] Set data transfer/receive format in SMR and SCMR Set value in BRR Wait [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0. Set the data transfer/receive format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 15.15 Sample SCI Initialization Flowchart Rev. 1.00 Sep. 21, 2006 Page 349 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev. 1.00 Sep. 21, 2006 Page 350 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode Rev. 1.00 Sep. 21, 2006 Page 351 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] [2] Read TDRE flag in SSR [2] [3] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 SCI initialization: The TxD pin is automatically designated as the transmit data output pin. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. No All data transmitted? Yes [3] Note: The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of transmission. This does not apply to the processing at step [4]. Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 End of transmission [4] Figure 15.17 Sample Serial Transmission Flowchart Rev. 1.00 Sep. 21, 2006 Page 352 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode Rev. 1.00 Sep. 21, 2006 Page 353 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception. [1] Initialization Start reception [1] [2] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Read ORER flag in SSR [2] Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4] [4] [5] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 End of reception [3] Error processing [6] [5] Note: The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of reception. This does not apply to the processing at step [6]. Overrun error processing Clear ORER flag in SSR to 0 End Figure 15.19 Sample Serial Reception Flowchart Rev. 1.00 Sep. 21, 2006 Page 354 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, check that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0, and then set the TE and RE bits to 1 simultaneously with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, check that the SCI has finished reception, and clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, set the TE and RE bits to 1 simultaneously with a single instruction. Rev. 1.00 Sep. 21, 2006 Page 355 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] [3] Read ORER flag in SSR Yes [3] Error processing ORER = 1 No [4] Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] No All data received? Yes [5] Clear TE and RE bits in SCR to 0 [6] End of transmission/reception Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. The SMR, SCR, SCMR, and BRR registers should not be written to during the period from the start to the end of transmission/reception. This does not apply to the processing at step [6]. SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically when the DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 1.00 Sep. 21, 2006 Page 356 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.7 Interrupt Sources Table 15.10 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 15.10 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Low Priority High Rev. 1.00 Sep. 21, 2006 Page 357 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.8 15.8.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 15.8.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.8.3 Mark State and Break Detection When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 15.8.5 Relation between Writing to TDR and TDRE Flag Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. Rev. 1.00 Sep. 21, 2006 Page 358 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.8.6 Restrictions on Using DTC When an external clock source is used as a synchronization clock, update TDR by the DTC and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 15.21). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: * When external clock is supplied, t must be more than four clock cycles. Figure 15.21 Example of Transmission using DTC in Clocked Synchronous Mode 15.8.7 (1) SCI Operations during Mode Transitions Transmission Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If a transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 15.22 shows a sample flowchart for mode transition during transmission. Figures 15.23 and 15.24 show the pin states during transmission. Before making a transition from the transmission mode using DTC transfer to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting Rev. 1.00 Sep. 21, 2006 Page 359 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC. Transmission All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 0. [2] Also clear TIE and TEIE to 0 when they are 1. Make transition to software standby mode etc. Cancel software standby mode etc. [3] [3] Module stop, watch, sub-active, and sub-sleep modes are included. Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 15.22 Sample Flowchart for Mode Transition during Transmission Rev. 1.00 Sep. 21, 2006 Page 360 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) Transmission start Transition to Software standby Transmission end software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 15.23 Pin States during Transmission in Asynchronous Mode (Internal Clock) Transition to Software standby software standby mode cancelled mode Transmission start Transmission end TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: * Initialized in software standby mode Figure 15.24 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) Rev. 1.00 Sep. 21, 2006 Page 361 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) (2) Reception Before making a transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 15.25 shows a sample flowchart for mode transition during reception. Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. RE = 0 [2] [2] Module stop, watch, sub-active, and subsleep modes are included. Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Yes Initialization No RE = 1 Start reception Figure 15.25 Sample Flowchart for Mode Transition during Reception Rev. 1.00 Sep. 21, 2006 Page 362 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.8.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.26. Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output Figure 15.26 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1. 1. 2. 3. 4. 5. End serial data transmission TE bit = 0 CKE1 bit = 1 C/A bit = 0 (switch to port output) CKE1 bit = 0 High output SCK/Port 1. Transmission end Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 15.27 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev. 1.00 Sep. 21, 2006 Page 363 of 658 REJ09B0310-0100 Section 15 Serial Communication Interface (SCI) 15.8.9 Notes on Register Writing during the Receive, Transmit, or Transfer Operation Once the TE or RE bit of the SCR register has been set to 1 to start the receive, transmit, or transfer operation, the SMR, SCR, SCMR, and BRR registers should not be written to. Rewriting the set value to these registers is also prohibited. However, this does not apply to the clearing of the TE or RE bit at the end of the receive, transmit, or transfer operation. These registers can always be read from. Rev. 1.00 Sep. 21, 2006 Page 364 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Section 16 I2C Bus Interface (IIC) This LSI has a two-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. 16.1 Features * Selection of addressing format or non-addressing format I2C bus format: addressing format with an acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only * Conforms to Philips I2C bus interface (I2C bus format) * Two ways of setting slave address (I2C bus format) * Start and stop conditions generated automatically in master mode (I2C bus format) * Selection of the acknowledge output level in reception (I2C bus format) * Automatic loading of an acknowledge bit in transmission (I2C bus format) * Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer. The wait request is cleared when the next transfer becomes possible. * Interrupt sources Data transfer end (including when a transition to transmit mode with I2C bus format occurs, when ICDR data is transferred, or during a wait state) Address match: When any slave address matches or the general call address is received in slave receive mode with I2C bus format (including address reception after loss of master arbitration) Start condition detection (in master mode) Stop condition detection (in slave mode) * Selection of 16 internal clocks (in master mode) IFIIC60A_000020020700 Rev. 1.00 Sep. 21, 2006 Page 365 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 * Direct bus drive (SCL/SDA pin) Two pins--P52/SCL0 and P47/SDA0--(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Two pins--P24/SCL1 and P23/SDA1--(normally CMOS pins) function as NMOS outputs when the bus drive function is selected. Voltage exceeding Vcc cannot be applied. Figure 16.1 shows a block diagram of the I2C bus interface. Figure 16.2 shows an example of I/O pin connections to external circuits. Since I2C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 24, Electrical Characteristics. ICXR SCL PS Clock control ICCR Noise canceler ICMR Arbitration decision circuit SDA Output data control circuit ICDRT ICDRS ICDRR Noise canceler Address comparator [Legend] ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register ICXR: I2C bus extended control register Slave address register SAR: SARX: Slave address register X Prescaler PS: SAR, SARX Interrupt generator Figure 16.1 Block Diagram of I2C Bus Interface Rev. 1.00 Sep. 21, 2006 Page 366 of 658 REJ09B0310-0100 Internal data bus Bus state decision circuit ICSR Interrupt request Section 16 I C Bus Interface (IIC) 2 VDD VCC VCC SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) This LSI SCL SDA SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 16.2 I2C Bus Interface Connections (Example: This LSI as Master) 16.2 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I2C bus interface. Table 16.1 Pin Configuration Channel 0 Symbol* SCL0 SDA0 1 Note: * SCL1 SDA1 Input/Output Input/Output Input/Output Input/Output Input/Output Function Serial clock input/output pin of IIC_0 Serial data input/output pin of IIC_0 Serial clock input/output pin of IIC_1 Serial data input/output pin of IIC_1 In the text, the channel subscript is omitted, and only SCL and SDA are used. Rev. 1.00 Sep. 21, 2006 Page 367 of 658 REJ09B0310-0100 SCL SDA Section 16 I C Bus Interface (IIC) 2 16.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). * * * * * * * * I2C bus control register (ICCR) I2C bus status register (ICSR) I2C bus data register (ICDR) I2C bus mode register (ICMR) Slave address register (SAR) Second slave address register (SARX) I2C bus extended control register (ICXR) DDC switch register (DDCSWR) (for IIC_0 only) I2C Bus Data Register (ICDR) 16.3.1 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. In master transmit mode with the I2C bus format, writing transmit data to ICDR should be performed after start condition detection. When the start condition is detected, previous write data is ignored. In slave transmit mode, writing should be performed after the slave addresses match and the TRS bit is automatically changed to 1. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next transmit data (the ICDRE flag is 0) after successful transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is transferred automatically from ICDRT to ICDRS by writing to ICDR. If I2C is in receive mode Rev. 1.00 Sep. 21, 2006 Page 368 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 (TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to ICDR in receive mode. Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR. If I2C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from ICDRS to ICDRR. Always set I2C to receive mode before reading from ICDR. If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. 16.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I2C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 369 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Slave Address 6 to 0 Set a slave address. Format Select Selects the communication format with the combination of the FSX bit in SARX. Refer to table 16.2. This bit should be set to 0 when general call address recognition is performed. 16.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the second slave address. If the LSI is in slave mode with the I2C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial Value 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Format Select X Selects the communication format together with the FS bit in SAR and the SW bit in DDCSWR. Refer to table 16.2. Description Second Slave Address 6 to 0 Set the second slave address. Rev. 1.00 Sep. 21, 2006 Page 370 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.2 Communication Format SAR FS 0 SARX FSX 0 Operating Mode I2C bus format * * 1 2 SAR and SARX slave addresses recognized General call address recognized SAR slave address recognized SARX slave address ignored General call address recognized SAR slave address ignored SARX slave address recognized General call address ignored SAR and SARX slave addresses ignored General call address ignored I C bus format * * * 1 0 I C bus format * * * 2 1 Clocked synchronous serial format * * * I2C bus format: addressing format with an acknowledge bit * Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only Rev. 1.00 Sep. 21, 2006 Page 371 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8 clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, refer to section 16.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Transfer Clock Select 2 to 0 These bits are used only in master mode. These bits select the required transfer rate, together with the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. Refer to table 16.3. th 2 2 Rev. 1.00 Sep. 21, 2006 Page 372 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 when a start condition is detected. The value returns to 000 at the end of a data transfer. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 1.00 Sep. 21, 2006 Page 373 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.3 I2C Transfer Rate STCR Bits 5 and 6 IICX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note: * Bit 5 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ICMR Bit 4 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 16 MHz 517 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz = 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz Outside the I C bus interface specifications (standard mode: max. 100 kHz; high-speed mode: max. 400 kHz) Rev. 1.00 Sep. 21, 2006 Page 374 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.3.5 I2C Bus Control Register (ICCR) ICCR controls the I2C bus interface and performs interrupt flag confirmation. Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I2C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU 1: Enables interrupts from the I C bus interface to the CPU. 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they lose 2 in a bus contention in master mode with the I C bus format. 2 In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer. 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 375 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 5 4 Bit Name MST TRS Initial Value 0 0 R/W R/W Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 3. When lost in bus contention in I C bus format master mode 4. When the SW bit in DDCSWR is changed from 1 to 0 [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing conditions 3 and 4) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing conditions 3 and 4) 3. When 1 is received as the R/W bit after the first frame 2 address matching in I C bus format slave mode 2 2 3 ACKE 0 R/W Acknowledge Bit Decision and Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the received acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Rev. 1.00 Sep. 21, 2006 Page 376 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 2 0 Bit Name BBSY SCP Initial Value 0 1 R/W R/W W Description Bus Busy Start Condition/Stop Condition Prohibit In master mode: * * Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled. In slave mode: * [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. [BBSY clearing condition] When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I2C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 0 is written, the data is not stored. 2 Rev. 1.00 Sep. 21, 2006 Page 377 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 1 Bit Name IRIC Initial Value 0 R/W Description 2 R/(W)* I2C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 16.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] I C bus format master mode: * When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission) When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) At the end of data transfer (rise of the 9th transmit/receive clock while no wait is inserted) When a slave address is received after bus arbitration is lost (the first frame after the start condition) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 When the AL flag is set to 1 after bus arbitration is lost while the ALIE bit is 1 When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th transmit/receive clock) When the general call address is detected (when 0 is received as the R/W bit and the ADZ flag in ICSR is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) while the ACKE bit is 1 When a stop condition is detected (when the STOP or ESTP flag in ICSR is set to 1) while the STOPIM bit is 0 2 * * * * * 2 I C bus format slave mode: * * * * Rev. 1.00 Sep. 21, 2006 Page 378 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 1 Bit Name IRIC Initial Value 0 R/W Description * * R/(W)* Clocked synchronous serial format mode: At the end of data transfer (rise of the 8th transmit/receive clock) When a start condition is detected When the ICDRE or ICDRF flag is set to 1 in any operating mode: * When a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the ICDRE flag is set to 1) When data is transferred among the ICDR register and buffer (when data is transferred from ICDRT to ICDRS in transmit mode and the ICDRE flag is set to 1, or when data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1) When 0 is written in IRIC after reading IRIC = 1 When ICDR is read from or written to by the DTC (This may not function as a clearing condition depending on the situation. For details, see the description of the DTC operation given below.) * [Clearing conditions] * * Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Sep. 21, 2006 Page 379 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I2C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Tables 16.4 and 16.5 show the relationship between the flags and the transfer states. Rev. 1.00 Sep. 21, 2006 Page 380 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.4 Flags and Transfer States (Master Mode) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 1 1 1 1 1 1 -- 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- 1 -- -- -- -- 0 1 -- -- Idle state (flag clearing required) Start condition detected Wait state Transmission end (ACKE = 1 and ACKB = 1) Transmission end with ICDRE = 0 ICDR write with the above state Transmission end with ICDRE = 1 ICDR write with the above state or after start condition detected Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF = 0 ICDR read with the above state Reception end with ICDRF = 1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Arbitration lost Stop condition detected 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- 1 0 1 0 1 1 1 0 0 1 0 0 0 0 0 -- 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 -- -- -- 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- 1 0 1 0 1 -- -- -- -- -- 0 1 0 -- 1 0 0 0 0 0 -- -- 0 0 1 0 0 0 0 0 -- -- -- -- -- 0 [Legend] 0: 0-state retained 1: 1-state retained --: Previous state retained Cleared to 0 0: Set to 1 1: Rev. 1.00 Sep. 21, 2006 Page 381 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.5 Flags and Transfer States (Slave Mode) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0 0 0 0 0 1/0 *1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 1 0 0 0 0 0 0 -- -- 1 0 1 1 Idle state (flag clearing required) Start condition detected SAR match in first frame (SARX SAR) General call address match in first frame (SARX H'00) SARS match in first frame (SAR SARX) Transmission end (ACKE = 1 and ACKB = 1) Transmission end with ICDRE = 0 ICDR write with the above state Transmission end with ICDRE = 1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF = 0 ICDR read with the above state 0 1 0 0 0 0 -- 1 1 0 1 1 0 1/0 *1 1 1 0 0 1 1 -- 0 0 0 1 1 0 1 0 0 -- -- -- -- 0 1 -- -- 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1/0 *1 -- -- -- 1/0 *2 -- -- -- -- -- -- 0 -- 0 0 -- 0 -- 0 0 0 0 1 0 0 0 0 0 0 0 -- -- 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1/0 *2 -- -- -- -- 0 -- 0 -- 0 -- -- 1 0 -- -- Rev. 1.00 Sep. 21, 2006 Page 382 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 2 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 -- -- 1/0 *2 -- -- -- -- 0 0 -- 0 0 -- 0 0 -- -- -- 1 0 1 -- -- -- Reception end with ICDRF = 1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Stop condition detected 0 -- 0 1/0 *3 0/1 *3 -- -- -- -- -- -- -- 0 [Legend] 0: 0-state retained 1: 1-state retained --: Previous state retained Cleared to 0 0: Set to 1 1: Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP = 1, STOP is 0, or when STOP = 1, ESTP is 0. Rev. 1.00 Sep. 21, 2006 Page 383 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.3.6 I2C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 16.4 and 16.5. Bit 7 Bit Name ESTP Initial Value 0 R/W Description 2 R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] * * When 0 is written in ESTP after reading ESTP = 1 When the IRIC flag in ICCR is cleared to 0 2 6 STOP 0 R/(W)* Normal Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer completion. [Clearing conditions] * * When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0 Rev. 1.00 Sep. 21, 2006 Page 384 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 5 Bit Name IRTR Initial Value 0 R/W Description R/(W)* I2C Bus Interface Continuous Transfer Interrupt Request Flag Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting conditions] I C bus format slave mode: * When the ICDRE or ICDRF flag in ICDR is set to 1 when AASX = 1 2 Master mode or clocked synchronous serial format mode with I2C bus format, or formatless mode: * * * 4 AASX 0 When the ICDRE or ICDRF flag is set to 1 When 0 is written after reading IRTR = 1 When the IRIC flag is cleared to 0 while ICE is 1 2 [Clearing conditions] R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 in SARX [Clearing conditions] * * * When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode Rev. 1.00 Sep. 21, 2006 Page 385 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 3 Bit Name AL Initial Value 0 R/W Description R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL = 0 * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device before the 2 I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1 2 When ALSL = 1 * * [Clearing conditions] * * 2 AAS 0 R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode Rev. 1.00 Sep. 21, 2006 Page 386 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 1 Bit Name ADZ Initial Value 0 R/W Description 2 R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 or FSX = 0 [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode If a general call address is detected while FS=1 and FSX=0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1). Rev. 1.00 Sep. 21, 2006 Page 387 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 0 Bit Name ACKB Initial Value 0 R/W R/W Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode [Clearing conditions] * * When 0 is received as the acknowledge bit when ACKE = 1 in transmit mode When 0 is written to the ACKE bit Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. If the ICSR register bit is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ACKB bit reading value. Write the ACKE bit to 0 to clear the ACKB flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and SDA is released to issue a stop condition by a master device. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Sep. 21, 2006 Page 388 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.3.7 DDC Switch Register (DDCSWR) DDCSWR controls the IIC internal latch clearance. Bit Bit Name Initial Value All 0 0 R/W R/W R Description Reserved The initial value should not be changed. 4 -- DDC Mode Switch Interrupt Flag Indicates an interrupt request to the CPU is generated when automatic format switching is executed for IIC_0. [Setting condition] When a falling edge is detected on the SCL pin when SWE =1 [Clearing condition] When 0 is written in IF after reading IF = 1 3 2 1 0 CLR3 CLR2 CLR1 CLR0 1 1 1 1 W* W* W* W* IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1. 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_0 internal latch cleared 0110: IIC_1 internal latch cleared 0111: IIC_0 and IIC_1 internal latches cleared 1---: Invalid setting When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the IIC module is initialized. These bits can only be written to; they are always read as 1. Write data to this bit is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Note: * This bit is always read as 1. 7 to 5 -- Rev. 1.00 Sep. 21, 2006 Page 389 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.3.8 I2C Bus Extended Control Register (ICXR) ICXR enables or disables the I2C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit 7 Bit Name STOPIM Initial Value 0 R/W R/W Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: Enables IRIC flag setting and interrupt generation when the stop condition is detected (STOP = 1 or ESTP = 1) in slave mode. 1: Disables IRIC flag setting and interrupt generation when the stop condition is detected. 6 HNDS 0 R/W Handshake Receive Operation Select Enables or disables continuous receive operation in receive mode. 0: Enables continuous receive operation 1: Disables continuous receive operation When the HNDS bit is cleared to 0, receive operation is performed continuously after data has been received successfully while ICDRF flag is 0. When the HNDS bit is set to 1, SCL is fixed to the low level and the next data transfer is disabled after data has been received successfully while the ICDRF flag is 0. The bus line is released and next receive operation is enabled by reading the receive data in ICDR. Rev. 1.00 Sep. 21, 2006 Page 390 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 5 Bit Name ICDRF Initial Value 0 R/W R Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] * When data is received successfully and transferred from ICDRS to ICDRR. 1. When data is received successfully while ICDRF = 0 (at the rise of the 9th clock pulse). 2. When ICDR is read successfully in receive mode after data was received while ICDRF = 1. [Clearing conditions] * * * When ICDR (ICDRR) is read. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. When ICDRF is set due to the condition (2) above, ICDRF is temporarily cleared to 0 when ICDR (ICDRR) is read; however, since data is transferred from ICDRS to ICDRR immediately, ICDRF is set to 1 again. Note that ICDR cannot be read successfully in transmit mode (TRS = 1) because data is not transferred from ICDRS to ICDRR. Be sure to read data from ICDR in receive mode (TRS = 0). Rev. 1.00 Sep. 21, 2006 Page 391 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 4 Bit Name ICDRE Initial Value 0 R/W R Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to. [Setting conditions] * * When the start condition is detected from the bus line 2 state with I C bus format or serial format. When data is transferred from ICDRT to ICDRS. 1. When data transmission completed while ICDRE = 0 (at the rise of the 9th clock pulse). 2. When data is written to ICDR in transmit mode after data transmission was completed while ICDRE = 1. [Clearing conditions] * * * * When data is written to ICDR (ICDRT). When the stop condition is detected with I2C bus format or serial format. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. 2 Note that if the ACKE bit is set to 1 with I C bus format thus enabling acknowledge bit decision, ICDRE is not set when data transmission is completed while the acknowledge bit is 1. When ICDRE is set due to the condition (2) above, ICDRE is temporarily cleared to 0 when data is written to ICDR (ICDRT); however, since data is transferred from ICDRT to ICDRS immediately, ICDRE is set to 1 again. Do not write data to ICDR when TRS = 0 because the ICDRE flag value is invalid during the time. Rev. 1.00 Sep. 21, 2006 Page 392 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Bit 3 Bit Name ALIE Initial Value 0 R/W R/W Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost. 0: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SCL pin is driven low by another device. 1: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SDA line is driven low by another device in idle state or after the start condition instruction was executed. 1 0 FNC1 FNC0 0 0 R/W R/W Function Bit Cancels some restrictions on usage. For details, refer to section 16.6, Usage Notes. 00: Restrictions on operation remaining in effect 01: Setting prohibited 10: Setting prohibited 11: Restrictions on operation canceled Rev. 1.00 Sep. 21, 2006 Page 393 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.4 Operation The I2C bus interface has an I2C bus format and a serial format. 16.4.1 I2C Bus Data Format The I2C bus format is an addressing format with an acknowledge bit. This is shown in figure 16.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 16.4. Figure 16.5 shows the I2C bus timing. The symbols used in figures 16.3 to 16.5 are explained in table 16.6. (a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Figure 16.3 I2C Bus Data Format (I2C Bus Format) FS=1 and FSX=1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Figure 16.4 I2C Bus Data Format (Serial Format) Rev. 1.00 Sep. 21, 2006 Page 394 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 16.5 I2C Bus Timing Table 16.6 I2C Bus Data Format Symbols Legend S SLA R/W A Start condition. The master device drives SDA from high to low while SCL is high Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR. Stop condition. The master device drives SDA from low to high while SCL is high DATA P Rev. 1.00 Sep. 21, 2006 Page 395 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.4.2 Initialization Initialize the IIC by the procedure shown in figure 16.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) (MSTPCRL) Set IICE = 1 in STCR Set DDCSWR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR Set STCR Set ICMR Set ICXR Set ICCR Cancel module stop mode Enable the CPU accessing to the IIC control register and data register Set IIC communication format (SWE, SW, IE, and IF) Enable SAR and SARX to be accessed Set the first and second slave addresses and IIC communication format (SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX) Enable ICMR and ICDR to be accessed Use SCL/SDA pin as an IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set communication format, wait insertion, and transfer rate (MLS, WAIT, CKS2 to CKS0) Enable interrupt (STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0) Set interrupt enable, transfer mode, and acknowledge decision (IEIC, MST, TRS, and ACKE) << Start transmit/receive operation >> Figure 16.6 Sample Flowchart for IIC Initialization Note: Be sure to modify the ICMR register after transmit/receive operation has been completed. If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be modified erroneously, thus causing incorrect operation. 16.4.3 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 16.7 shows the sample flowchart for the operations in master transmit mode. Rev. 1.00 Sep. 21, 2006 Page 396 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Start Initialize IIC Read BBSY flag in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC flag in ICCR No [5] Wait for a start condition generation IRIC = 1? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB bit in ICSR [11] Determine end of tranfer No End of transmission? (ACKB = 1?) [1] Initialization [3] Select master transmit mode. [4] Start condition issuance [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC flag continuously.) [7] Wait for 1 byte to be transmitted. No [8] Test the acknowledge bit transferred from the slave device. No Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC flag continuously.) Yes Clear IRIC flag in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance Figure 16.7 Sample Flowchart for Operations in Master Transmit Mode Rev. 1.00 Sep. 21, 2006 Page 397 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The transmission procedure and operation, by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. 2. 3. 4. Initialize the IIC as described in section 16.4.2, Initialization. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TRS to 1 in ICCR to select master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmission clock and the data written to ICDR. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission. Rev. 1.00 Sep. 21, 2006 Page 398 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Start condition generation SCL (master output) SDA (master output) SDA (slave output) ICDRE 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6 Slave address [5] Data 1 IRIC Interrupt request Interrupt request IRTR ICDRT Address + R/W Data 1 ICDRS Address + R/W Data 1 Note:* Data write in ICDR prohibited User processing [4] BBSY set to 1 [6] ICDR write SCP cleared to 0 (start condition issuance) [6] IRIC clear [9] ICDR write [9] IRIC clear Figure 16.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 1.00 Sep. 21, 2006 Page 399 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Stop condition issuance SCL (master output) 8 9 1 Bit 7 [7] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [10] A 9 SDA Bit 0 (master output) Data 1 SDA (slave output) ICDRE IRIC IRTR ICDR Data 2 Data 1 Data 2 User processing [9] ICDR write [9] IRIC clear [11] ACKB read [12] IRIC clear [12] Set BBSY=1and SCP=0 (Stop condition issuance) Figure 16.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) 16.4.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Rev. 1.00 Sep. 21, 2006 Page 400 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 (1) Receive Operation Using the HNDS Function (HNDS = 1) Figure 16.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1). Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 1 in ICXR Clear IRIC flag in ICCR [1] Select receive mode. Last receive? No Read ICDR Yes [2] Start receiving. The first read is a dummy read. [5] Read the receive data (for the second and subsequent read) Read IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR [3] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock for the receive frame) [4] Clear IRIC flag. Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? [6] Set acknowledge data for the last reception. [7] Read the receive data. Dummy read to start receiving if the first frame is the last receive data. [8] Wait for 1 byte to be received. Yes Clear IRIC flag in ICCR Set TRS = 1 in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End [9] Clear IRIC flag. [10] Read the receive data. [11] Set stop condition issuance. Generate stop condition. Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) Rev. 1.00 Sep. 21, 2006 Page 401 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2. When ICDR is read (dummy data read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. (Data from the SDA pin is sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.) 3. The master device drives SDA low to return the acknowledge data at the 9th receive clock pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading. 4. Clear the IRIC flag to determine the next interrupt. Go to step [6] to halt reception operation if the next frame is the last receive data. 5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock continuously to receive the next data. Data can be received continuously by repeating steps [3] to [5]. 6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception. 7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock to receive data. 8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the rise of the 9th receive clock pulse. 9. Clear the IRIC flag to 0. 10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0. 11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 1.00 Sep. 21, 2006 Page 402 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Master transmit mode Master receive mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR 9 A 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Data 1 Data 2 Undefined value Data 1 User processing [1] TRS=0 clear [1] IRIC clear [2] ICDR read (Dummy read) [4] IRIC clear [5] ICDR read (Data 1) Figure 16.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) SCL is fixed low until stop condition is issued 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [8] A 9 SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Data 1 Data 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Stop condition generation Data 2 Data 3 Data 3 [10] ICDR read (Data 3) [11] Set BBSY=0 and SCP=0 (Stop condition instruction issuance) User processing [4] IRIC clear [7] ICDR read (Data 2) [6] Set ACKB = 1 [9] IRIC clear Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) Rev. 1.00 Sep. 21, 2006 Page 403 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 (2) Receive Operation Using the Wait Function Figures 16.13 and 16.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [4] Determine end of reception IRTR = 1? Yes Last receive? No Read ICDR Clear IRIC flag in ICCR [5] Read the receive data. [6] Clear IRIC flag. (to end the wait insertion) Yes [1] Select receive mode. Read IRIC flag in ICCR No IRIC = 1? Yes No Set ACKB = 1 in ICSR Wait for one clock pulse Set TRS = 1 in ICCR Read ICDR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [8] Wait for TRS setting [9] Set TRS for stop condition issuance [10] Read the receive data. [11] Clear IRIC flag. Read IRIC flag in ICCR No IRIC=1? Yes IRTR=1? No Clear IRIC flag in ICCR Yes [12] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [13] Determine end of reception [14] Clear IRIC. (to end the wait insertion) [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data. [17] Generate stop condition Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY= 0 and SCP= 0 in ICCR End Figure 16.13 Sample Flowchart for Operations in Master Receive Mode (receiving multiple bytes) (WAIT = 1) Rev. 1.00 Sep. 21, 2006 Page 404 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 0 in ICMR [1] Select receive mode. Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Yes Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [9] Set TRS for stop condition issuance [14] Clear IRIC flag. (to end the wait insertion) [12] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock) Read IRIC flag in ICCR No IRIC = 1? Yes Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data [17] Generate stop condition End Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (receiving a single byte) (WAIT = 1) Rev. 1.00 Sep. 21, 2006 Page 405 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 16.14. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data is read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. 3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 4. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception. 5. If IRTR flag is 1, read ICDR receive data. 6. Clear the IRIC flag. When the flag is set as the first case in step [3], the master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [3] to [6]. 7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception. 8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock pulse for the next receive data. 9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value becomes valid when the rising edge of the next 9th clock pulse is input. 10. Read the ICDR receive data. Rev. 1.00 Sep. 21, 2006 Page 406 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 11. Clear the IRIC flag to 0. 12. The IRIC flag is set to 1 in either of the following cases. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 13. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state. Execute step [12] to read the IRIC flag to detect the end of reception. 15. Clear the WAIT bit in ICMR to cancel the wait mode. Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition may not be issued correctly.) 16. Read the last ICDR receive data. 17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 1.00 Sep. 21, 2006 Page 407 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Master tansmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 SDA (slave output) SDA (master output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A [3] Bit 7 Bit 6 Bit 5 Data 2 Bit 4 Bit 3 IRIC IRTR [4]IRTR=0 [4] IRTR=1 ICDR Data 1 User processing [1] TRS cleared to 0 IRIC cleard to 0 [2] ICDR read (dummy read) [6] IRIC clear [5] ICDR read [6] IRIC clear (to end wait insertion) (Data 1) Figure 16.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) [8] Wait for one clock pulse Stop condition generation SCL (master output) 8 9 1 Bit 7 [3] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [12] A [12] 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR [4] IRTR=0 Data 3 [4] IRTR=1 [13] IRTR=0 [13] IRTR=1 Data 1 Data 2 Data 3 [15] WAIT cleared to 0, IRIC clear [14] IRIC clear (to end wait [17] Stop condition insertion) issuance [16] ICDR read (Data 3) User processing [6] IRIC clear (to end wait insertion) [11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1 [7] Set ACKB=1 Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) Rev. 1.00 Sep. 21, 2006 Page 408 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.4.5 Slave Receive Operation In I2C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. (1) Receive Operation Using the HNDS Function (HNDS = 1) Figure 16.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1). Rev. 1.00 Sep. 21, 2006 Page 409 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Clear IRIC flag in ICCR ICDRF = 1? No [2] Read the receive data remaining unread. [1] Initialization. Select slave receive mode. Yes Read ICDR, clear IRIC flag Clear IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No Yes Last reception? No Read ICDR Read IRIC flag in ICCR No IRIC = 1? [8] Clear IRIC flag. [10] Read the receive data. The first read is a dummy read. [5] to [7] Wait for the reception to end. Yes Slave transmit mode Yes General call address processing * Description omitted [8] Clear IRIC flag [3] to [7] Wait for one byte to be received (slave address + R/W) Yes Clear IRIC flag in ICCR Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? Yes ESTP = 1 or STOP = 1? Yes [9] Set acknowledge data for the last reception. [10] Read the receive data. [5] to [7] Wait for reception end. [11] Detect stop condition. [12] Check STOP bit. No Clear IRIC flag in ICCR [8] Clear IRIC flag. Clear IRIC flag in ICCR End [12] Clear IRIC flag. Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) Rev. 1.00 Sep. 21, 2006 Page 410 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive clock pulse until data is read from ICDR. 8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0. 9. If the next frame is the last receive frame, set the ACKB bit to 1. 10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the master device to transfer the next data. Receive operations can be performed continuously by repeating steps [5] to [10]. 11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. 12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0. Rev. 1.00 Sep. 21, 2006 Page 411 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) IRIC ICDRF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1 1 2 2 3 3 4 4 5 5 6 6 7 7 [7] SCL is fixed low until ICDR is read 8 8 9 9 1 1 2 2 Bit 2 Bit 1 Bit 0 R/W [6] A Interrupt request occurrence Bit 7 Bit 6 Data 1 Slave address ICDRS Address+R/W ICDRR Undefined value Address+R/W User processing [2] ICDR read [8] IRIC clear [10] ICDR read (dummy read) Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) Stop condition generation [7] SCL is fixed low until ICDR is read SCL (master output) SCL (slave output) SDA (master output) Data (n-1) SDA (slave output) IRIC Bit 0 [6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data (n) [6] [11] 8 9 1 2 3 4 5 [7] SCL is fixed low until ICDR is read 6 7 8 9 A A ICDRF ICDRS Data (n-1) Data (n) ICDRR Data (n-2) Data (n-1) Data (n) User processing [8] IRIC clear [5] ICDR read (Data (n-1)) [9] Set ACKB=1 [8] IRIC clear [10] ICDR read (Data (n)) [12] IRIC clear Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) Rev. 1.00 Sep. 21, 2006 Page 412 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 (2) Continuous Receive Operation Figure 16.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Slave receive mode Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No No * n: Address + total number of bytes received Yes Yes General call address processing * Description omitted [8] Clear IRIC [3] to [7] Wait for one byte to be received (slave address + R/W) (Set IRIC at the rise of the 9th clock) No [2] Read the receive data remaining unread. [1] Select slave receive mode. Slave transmit mode (n-2)th-byte reception? Yes Wait for one frame Set ACKB = 1 in ICSR [9] Wait for ACKB setting and set acknowledge data for the last reception (after the rise of the 9th clock of (n-1)th byte data) No [10] Read the receive data. The first read is a dummy read. ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1? Yes ESTP = 1 or STOP = 1? No Clear IRIC in ICCR [11] Wait for one byte to be received (Set IRIC at the rise of the 9th clock) Yes [12] Detect stop condition [13] Clear IRIC ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR End No [14] Read the last receive data [15] Clear IRIC Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) Rev. 1.00 Sep. 21, 2006 Page 413 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W) in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, the IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. 8. Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0. 9. If the next read data is the third last receive frame, wait for at least one frame time to set the ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive frame. 10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0. 11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to ICDRR due to ICDR read operation, the IRIC and ICDRF flags are set to 1. 12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last receive data. 13. Clear the IRIC flag to 0. Receive operations can be performed continuously by repeating steps [9] to [13]. 14. Confirm that the ICDRF flag is set to 1, and read ICDR. 15. Clear the IRIC flag. Rev. 1.00 Sep. 21, 2006 Page 414 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Start condition issuance SCL (master output) SDA (master output) SDA (slave output) 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [6] A 9 1 Bit 7 2 Bit 6 Data 1 3 Bit 5 4 Bit 4 Slave address IRIC ICDRF ICDRS Address+R/W [7] Data 1 ICDRR Address+R/W User processing [8] IRIC clear [10] ICDR read Figure 16.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0) Stop condition detection 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL (master output) SDA (master output) Bit 0 Data n-2 SDA (slave output) IRIC [11] A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data n-1 [11] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data n [11] [11] A A ICDRF ICDRS Data n-2 Data n-1 Data n Data n ICDRR Data n-2 [9] Wait for one frame Data n-1 User processing [13] IRIC clear [13] IRIC clear [10] ICDR read (Data n-2) [9] Set ACKB = 1 [10] ICDR read (Data n-1) [13] IRIC clear [14] ICDR read (Data n) [15] IRIC clear Figure 16.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0) Rev. 1.00 Sep. 21, 2006 Page 415 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 16.23 shows the sample flowchart for the operations in slave transmit mode. Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR No End of transmission (ACKB = 1)? Yes Clear IRIC in ICCR Clear ACKE to 0 in ICCR (ACKB=0 clear) Set TRS = 0 in ICCR Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR End [6] Clear IRIC in ICCR [7] Clear acknowledge bit data [8] Set slave receive mode. [9] Dummy read (to release the SCL line). [10] Wait for stop condition [4] Determine end of transfer. [1], [2] If the slave address matches to the address in the first frame following the start condition detection and the R/W bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [3], [5] Set transmit data for the second and subsequent bytes. [3], [4] Wait for 1 byte to be transmitted. Figure 16.23 Sample Flowchart for Slave Transmit Mode Rev. 1.00 Sep. 21, 2006 Page 416 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit 9th clock until ICDR data is written, to disable the master device to output the next transfer clock. 3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again. The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. 4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS, transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device drives SCL low from the fall of the 9th transmit clock until data is written to ICDR. 5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. Transmit operations can be performed continuously by repeating steps [4] and [5]. 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SCL on the slave side. Rev. 1.00 Sep. 21, 2006 Page 417 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0. Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 [2] Data 1 [4] Data 2 SDA (master output) R/W A IRIC ICDRE ICDR User processing [3] IRIC clear [3] ICDR write [3] IRIC clear Data 1 Data 2 [5] IRIC clear [5] ICDR write Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 1.00 Sep. 21, 2006 Page 418 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 16.25 to 16.27 show the IRIC set timing and SCL control. When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 2 3 SDA 7 8 A 1 2 3 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL 7 8 9 1 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 16.25 IRIC Setting Timing and SCL Control (1) Rev. 1.00 Sep. 21, 2006 Page 419 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 2 3 SDA 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL 8 9 1 SDA 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 16.26 IRIC Setting Timing and SCL Control (2) Rev. 1.00 Sep. 21, 2006 Page 420 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL 7 8 1 2 3 4 SDA 7 8 1 2 3 4 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 16.27 IRIC Setting Timing and SCL Control (3) 16.4.8 Operation Using DTC This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0, the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the acknowledge bit value. If the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set when data transmission is completed with the acknowledge bit value of 0, and if the ACKE bit is 1, only the IRIC flag is set when data transmission is completed with the acknowledge bit value of 1. When initiated, the DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, the DTC is not initiated, thus allowing an interrupt to be generated if enabled. Rev. 1.00 Sep. 21, 2006 Page 421 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The acknowledge bit may indicate specific events such as completion of receive data processing for some receiving devices, and for other receiving devices, the acknowledge bit may be fixed at 1, indicating no specific events. The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 16.7 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Table 16.7 Examples of Operation Using DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing -- Transmission by DTC (ICDR write) -- Not necessary 1st time: Clearing by CPU 2nd time: Stop condition issuance by CPU Processing by CPU (ICDR read) Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Not necessary -- Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary -- Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of stop condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Setting of number of DTC transfer data frames Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) Rev. 1.00 Sep. 21, 2006 Page 422 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.4.9 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.28 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock cycle Sampling clock Figure 16.28 Block Diagram of Noise Canceler 16.4.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch Register (DDCSWR). (1) Scope of Initialization The initialization executed by this function covers the following items: * ICDRE and ICDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) Rev. 1.00 Sep. 21, 2006 Page 423 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, and ICXR (except for the ICDRE and ICDRF flags)) * Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR * The value of the ICMR bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) Notes on Initialization * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. * Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers. Rev. 1.00 Sep. 21, 2006 Page 424 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.5 Interrupt Sources The IIC has interrupt sources, IICI0 and IICI1. Table 16.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bit in ICCR, and are sent to the interrupt controller independently. An IICI interrupt can activate the DTC to allow data transfer. Table 16.8 IIC Interrupt Sources Channel 0 1 Name IICI0 IICI1 Enable Bit IEIC IEIC Interrupt Source I C bus interface interrupt request I2C bus interface interrupt request 2 Interrupt Flag IRIC IRIC DTC Activation Possible Possible Priority High Low 16.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I2C bus, neither condition will be output correctly. To output the stop condition followed by the start condition*, after issuing the instruction that generates the start condition, read DR in each I2C bus output pin, and check that SCL and SDA are both low. The pin states can be monitored by reading DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. Note: * An illegal procedure in the I2C bus specification. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing to ICDR. Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Rev. 1.00 Sep. 21, 2006 Page 425 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.9 I2C Bus Timing (SCL and SDA Outputs) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO 6tcyc when IICX is 0, 12tcyc when 1. Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28tcyc to 256tcyc 0.5tSCLO 0.5tSCLO 0.5tSCLO - 1tcyc 0.5tSCLO - 1tcyc 1tSCLO 0.5tSCLO + 2tcyc 1tSCLLO - 3tcyc 1tSCLL - (6tcyc or 12tcyc*) 3tcyc ns Unit ns ns ns ns ns ns ns ns Notes See figure 24.26. 4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 24, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 16.10. Rev. 1.00 Sep. 21, 2006 Page 426 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.10 Permissible SCL Rise Time (tsr) Values Time Indication [ns] tcyc IICX Indication 0 7.5 tcyc Standard mode High-speed mode 1 17.5 tcyc Standard mode High-speed mode I C Bus Specification (Max.) = 8 MHz = 10 MHz = 16 MHz = 20 MHz 1000 300 1000 300 937 750 468 375 875 2 6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in table 16.9. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Rev. 1.00 Sep. 21, 2006 Page 427 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Table 16.11 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) -1000 -300 -250 -250 -1000 -300 -250 -250 -1000 -300 -1000 -300 -1000 -300 -1000 -300 I C Bus Specification = 8 MHz (Min.) 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 4000 950 4750 1000* 3875* 825* 1 1 2 Item tSCLHO tcyc Indication 0.5 tSCLO (-tSr) Standard mode High-speed mode = 10 MHz 4000 950 4750 1000* 3900* 850* 1 1 = 16 MHz 4000 950 4750 1000* 3938* 888* 1 1 = 20 MHz 4000 950 4750 1000* 3950* 900* 1 1 tSCLLO 0.5 tSCLO (-tSf) Standard mode High-speed mode tBUFO 0.5 tSCLO -1 tcyc Standard mode (-tSr) High-speed mode 0.5 tSCLO -1 tcyc Standard mode (-tSf) High-speed mode 1 tSCLO (-tSr) Standard mode High-speed mode 1 1 1 1 tSTAHO 4625 875 9000 2200 4250 1200 3325 625 2200 -500* 1 4650 900 9000 2200 4200 1150 3400 700 2500 -200* 1 4688 938 9000 2200 4125 1075 3513 813 2950 250 4700 950 9000 2200 4100 1050 3550 850 3100 400 tSTASO tSTOSO 0.5 tSCLO + 2 tcyc (-tSr) Standard mode High-speed mode Standard mode High-speed mode Standard mode High-speed mode tSDASO 1 tSCLLO* (master) -3 tcyc (-tSr) tSDASO (slave) 3 3 1 tSCLL* 2 -12 tcyc* (-tSr) Rev. 1.00 Sep. 21, 2006 Page 428 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) Standard mode High-speed mode 0 0 I C Bus Specification = 8 MHz (Min.) 0 0 375 375 2 Item tSDAHO tcyc Indication 3 tcyc = 10 MHz 300 300 = 16 MHz 188 188 = 20 MHz 150 150 Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6 tcyc). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). 7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR (ICDRR), and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released, then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.29 (after confirming that the BBSY bit in ICCR has been cleared to 0). Rev. 1.00 Sep. 21, 2006 Page 429 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Stop condition (a) SDA SCL Internal clock BBSY bit Bit 0 8 A 9 Start condition Master receive mode ICDR read disabled period Execution of instruction for issuing stop condition (write 0 to BBSY and SCP) Confirmation of stop condition issuance (read BBSY = 0) Start condition issuance Figure 16.29 Notes on Reading Master Receive Data Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 8. Notes on start condition issuance for retransmission Figure 16.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated. Rev. 1.00 Sep. 21, 2006 Page 430 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 IRIC = 1? Yes Clear IRIC in ICCR No [1] [1] Wait for end of 1-byte transfer [2] Determine whether SCL is low Read SCL pin SCL = Low? Yes Set BBSY = 1, SCP = 0 (ICCR) [3] No [2] [3] Issue start condition instruction for retransmission [4] Determine whether start condition is generated or not [5] Set transmit data (slave address + R/W) Note: Program so that processing from [3] to [5] is executed continuously. IRIC = 1? Yes Write transmit data to ICDR No [4] [5] Start condition generation (retransmission) SCL 9 SDA ACK Bit7 IRIC [5] ICDR write (transmit data) [4] IRIC determination [1] IRIC determination [3] (Retransmission) Start condition instruction issuance [2] Determination of SCL = Low Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. Rev. 1.00 Sep. 21, 2006 Page 431 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 9. Note on when I2C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low. 9th clock VIH Secures a high period SCL SCL is detected as low because the rise of the waveform is delayed SDA Stop condition generation IRIC [1] SCL = low determination [2] Stop condition instruction issuance Figure 16.31 Stop Condition Issuance Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 10. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be inserted by driving the SCL pin low is used when the wait function is used in I2C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below. If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time, the SDA level may change before the SCL goes low, which may generate a start or stop condition erroneously. Rev. 1.00 Sep. 21, 2006 Page 432 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Secures a high period SCL VIH SCL = low detected SDA IRIC [1] SCL = low determination [2] IRIC clear Figure 16.32 IRIC Flag Clearing Timing When WAIT = 1 Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 11. Note on ICDR read and ICCR access in slave transmit mode In I2C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 16.33. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. To handle interrupts securely, be sure to keep either of the following conditions. Read ICDR data that has been received so far or read/write from/to ICCR before starting the receive operation of the next slave address. Monitor the BC2 to BC0 bit counter in ICMR; when the count is B'000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to ICCR during the time other than the shaded time. Rev. 1.00 Sep. 21, 2006 Page 433 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Waveform at problem occurrence SDA R/W A ICDR write Bit 7 SCL 8 9 TRS bit Address reception Data transmission ICDR read and ICCR read/write are disabled (6 system clock period) The rise of the 9th clock is detected Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 12. Note on TRS bit setting in slave mode In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 16.34), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 16.34), the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the stop condition is detected. Therefore, when the address is received after the restart condition is input without the stop condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 16.34. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR. Rev. 1.00 Sep. 21, 2006 Page 434 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Restart condition (a) SDA (b) A SCL 8 9 1 2 3 4 5 6 7 8 9 TRS Data transmission Address reception TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected The rise of the 9th clock is detected Figure 16.34 TRS Bit Set Timing in Slave Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 13. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode or write to ICDR after setting transmit mode. 14. Note on ACKE and TRS bits in slave mode In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. Similarly, if the start condition or address is transmitted from the master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt source even when the address does not match. To use the I2C bus interface module in slave mode, be sure to follow the procedures below. A. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB bit to 0. Rev. 1.00 Sep. 21, 2006 Page 435 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 B. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 16.23, in order to switch from slave transmit mode to slave receive mode. 15. Note on Arbitration Lost in Master Mode The I2C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX register, the I2C bus interface erroneously recognizes that the address call has occurred. (See figure 16.35.) In multi-master mode, a bus conflict could happen. When the I2C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. * Arbitration is lost * The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data does not match Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A DATA2 A DATA3 A Data contention bus interface (Slave receive mode) I2C S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device. Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost Rev. 1.00 Sep. 21, 2006 Page 436 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 16.6.1 Note on Wait Function in Master Mode While the WAIT bit in ICMR is set to 1 and WAIT in master mode, if the interrupt flag of the IRIC bit is cleared from 1 to 0 between the falling edge of the 7th clock and the falling edge of the 8th clock, the clock pulse of the 9th clock may be output continuously due to the failure to insert a wait after the falling edge of the 8th clock. When the wait function is used in master mode, clear the IRIC flag after the IRIC flag is set to 1 on the falling edge of the 9th clock and before the rising edge of the 7th clock (the counter value of BC2 to BC0 should be 2 or greater). If the clearing of the IRIC flag is delayed due to the interrupt or other processes and the value of the RC counter is changed to 1 or 0, confirm that the SCL pins are in the L state after the counter values of BC2 to BC0 are cleared to 0, and then clear the IRIC flag (see figure 16.36). SDA A Transmit/receive data A Transmit/ receive data SCL 9 1 2 3 4 5 6 7 8 Confirm SCL = L 9 1 2 3 BC2 to BC0 0 7 6 5 4 3 2 1 0 Clear IRIC 7 6 5 When BC2 to BC0 2, clear IRIC IRIC (operation example) IRIC flag clearing possible IRIC flag clearing possible IRIC flag clear impossible Figure 16.36 IRIC Flag Clear Timing in Wait Operation Note: This limitation on use can be cleared by setting the FNC1 and FNC0 bits in ICXR to B'11. 16.6.2 Module Stop Mode Setting The IIC operation can be enabled or disabled using the module stop control register. The initial setting is for the IIC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 437 of 658 REJ09B0310-0100 Section 16 I C Bus Interface (IIC) 2 Rev. 1.00 Sep. 21, 2006 Page 438 of 658 REJ09B0310-0100 Section 17 A/D Converter Section 17 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels to be selected. 17.1 Features * 10-bit resolution * Input channels: Eight analog input channels * Analog conversion voltage range can be specified using the analog power supply voltage pin (AVCC) as an analog reference voltage. * Conversion time: 13.4 s per channel (at 20-MHz operation) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on one to four channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of A/D conversion start Software Timer (8-bit timer) conversion start trigger External trigger signal (ADTRG) * Interrupt source A/D conversion end interrupt (ADI) request can be generated ADCMS33A_000020020300 Rev. 1.00 Sep. 21, 2006 Page 439 of 658 REJ09B0310-0100 Section 17 A/D Converter A block diagram of the A/D converter is shown in figure 17.1. Module data bus Bus interface Internal data bus AVCC 10-bit D/A AVSS Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 AN1 Multiplexer + /8 AN2 AN3 AN4 AN5 AN6 AN7 Comparator Sample-and-hold circuit Control circuit /16 ADI interrupt signal Conversion start trigger from 8-bit timer ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 17.1 Block Diagram of A/D Converter Rev. 1.00 Sep. 21, 2006 Page 440 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.2 Input/Output Pins Table 17.1 summarizes the pins used by the A/D converter. The eight analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 17.1 Pin Configuration Pin Name Symbol I/O Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Group 1 analog input pins Function Analog block power supply Analog block ground and reference voltage Group 0 analog input pins Analog power supply AVCC pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG Rev. 1.00 Sep. 21, 2006 Page 441 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.3 Register Descriptions The A/D converter has the following registers. * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) A/D Data Registers A to D (ADDRA to ADDRD) 17.3.1 There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers which store a conversion result for each channel are shown in table 17.2. The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0. The data bus between the CPU and A/D converter is eight bits wide. The upper byte can be read directly from the CPU. However, when the lower byte is read from, data that was transferred to a temporary register at reading of the upper byte is read. Accordingly, when reading from ADDR, access in word units or access upper byte first, and then lower byte. Table 17.2 Analog Input Channels and Corresponding ADDR Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD Rev. 1.00 Sep. 21, 2006 Page 442 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D converter operation. Bit 7 Initial Bit Name Value ADF 0 R/W Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode When 0 is written after reading ADF = 1 When DTC is activated by an ADI interrupt and ADDR is read [Clearing conditions] * * 6 5 ADIE ADST 0 0 R/W R/W A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1. A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects the A/D converter operating mode. 0: Single mode 1: Scan mode Switch the operating mode when ADST = 0. 3 CKS 0 R/W Clock Select Sets A/D conversion time. 0: Conversion time is 266 states (max) 1: Conversion time is 134 states (max) (when the system clock () is 16 MHz or lower) Switch conversion time while the ADST bit is cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 443 of 658 REJ09B0310-0100 Section 17 A/D Converter Bit 2 1 0 Initial Bit Name Value CH2 CH1 CH0 0 0 0 R/W R/W R/W R/W Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 When SCAN = 1 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5 110: AN4 to AN6 111: AN4 to AN7 Switch input channels when ADST = 0. Note: * Only 0 can be written for clearing the flag. 17.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit 7 6 Initial Bit Name Value TRGS1 TRGS0 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 Enable the start of A/D conversion by a trigger signal. Set these bits only while A/D conversion is stopped (ADST = 0). 00: A/D conversion start by external trigger is disabled 01: Setting prohibited 10: A/D conversion start by conversion trigger from TMR 11: A/D conversion start by ADTRG pin 5 to 0 All 1 R/W Reserved The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 444 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set at the same time the operating mode or analog input channel is changed. 17.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0, and the A/D converter enters wait state. 17.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (max. four channels). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts on the first channel in the group (AN0 when the CH2 bit in ADCSR is 0, or AN4 when the CH2 bit in ADCSR is 1). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion from the first channel in the group starts again. 4. The ADST bit is not automatically cleared to 0 so steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. Rev. 1.00 Sep. 21, 2006 Page 445 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 17.2 shows the A/D conversion timing. Table 17.3 indicates the A/D conversion time. As indicated in figure 17.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of write to ADCSR. The total conversion time therefore varies within the ranges indicated in table 17.3. In scan mode, the values shown in table 17.3 become those for the first conversion time. For the second and subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states (fixed) when CKS = 1. Use the conversion time of 134 states only when the system clock () is 16 MHz or lower. Rev. 1.00 Sep. 21, 2006 Page 446 of 658 REJ09B0310-0100 Section 17 A/D Converter (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 17.2 A/D Conversion Timing Table 17.3 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. 10 259 Typ. 63 Max. 17 266 Min. 6 131 CKS = 1* Typ. 31 Max. 9 134 Notes: Values in the table indicate the number of states. * in the table indicates that the system clock () is 16 MHz or lower. Rev. 1.00 Sep. 21, 2006 Page 447 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 17.3 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 17.3 External Trigger Input Timing Rev. 1.00 Sep. 21, 2006 Page 448 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. If the ADF bit in ADCSR has been set to 1 after A/D conversion ends and the ADIE bit is set to 1, an ADI interrupt request is enabled. The ADI interrupt can be used to activate the on-chip DTC. Table 17.4 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF DTC Activation Enable 17.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristics when the digital output changes from the minimum voltage value B'00 0000 0000 (H'000) to B'00 0000 0001 (H'001) (see figure 17.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristics when the digital output changes from B'11 1111 1110 (H'3FE) to B'11 1111 1111 (H'3FF) (see figure 17.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 17.5). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 1.00 Sep. 21, 2006 Page 449 of 658 REJ09B0310-0100 Section 17 A/D Converter Digital output H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 17.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 17.5 A/D Conversion Accuracy Definitions Rev. 1.00 Sep. 21, 2006 Page 450 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.7 17.7.1 Usage Notes Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/s or greater) (see figure 17.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 17.7.2 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not interfere with digital signals on the mounting board, so acting as antennas. This LSI Sensor output impedance up to 5 k Sensor input Low-pass filter C up to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 17.6 Example of Analog Input Circuit Rev. 1.00 Sep. 21, 2006 Page 451 of 658 REJ09B0310-0100 Section 17 A/D Converter 17.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ANn AVCC (n = 0 to 7). * Relation between AVCC, VSS and VCC, VSS For the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS, but AVCC = VCC is not necessary and which one is greater does not matter. Even when the A/D converter is not used, the ACC and AVSS pins must on no account be left open. 17.7.4 Notes on Board Design * In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input pins (AN0 to AN7) and analog power supply voltage (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable ground (VSS) on the board. 17.7.5 Notes on Noise Countermeasures A protection circuit connected to prevent damage of the analog input pins (AN0 to AN7) due to an abnormal voltage such as an excessive surge should be connected between AVCC and AVSS, as shown in figure 17.7. Also, the bypass capacitors connected to AVCC and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Rev. 1.00 Sep. 21, 2006 Page 452 of 658 REJ09B0310-0100 Section 17 A/D Converter AVCC Rin *2 *1 100 AN0 to AN7 0.1 F AVSS Notes: Values are reference values. *1 10 F 0.01 F *2 Rin: Input impedance Figure 17.7 Example of Analog Input Protection Circuit 10 k AN0 to AN7 20 pF To A/D converter Note: Values are reference values. Figure 17.8 Analog Input Pin Equivalent Circuit 17.7.6 Module Stop Mode Setting A/D converter operation can be enabled or disabled by the module stop control register. In the initial state, A/D converter operation is disabled. Access to A/D converter registers is enabled when module stop mode is cancelled. For details, see section 22, Power-Down Modes. Rev. 1.00 Sep. 21, 2006 Page 453 of 658 REJ09B0310-0100 Section 17 A/D Converter Rev. 1.00 Sep. 21, 2006 Page 454 of 658 REJ09B0310-0100 Section 18 RAM Section 18 RAM This LSI has 8 Kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Rev. 1.00 Sep. 21, 2006 Page 455 of 658 REJ09B0310-0100 Section 18 RAM Rev. 1.00 Sep. 21, 2006 Page 456 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Section 19 Flash Memory (0.18-m F-ZTAT Version) The flash memory has the following features. Figure 19.1 shows a block diagram of the flash memory. 19.1 * Size Features Product Classification H8S/2125 R4F2125 ROM Size 512 Kbytes ROM Addresses H'000000 to H'07FFFF (mode 2) H'0000 to H'DFFF (mode 3) * Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting at initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation. The user MAT is initiated at a power-on reset in user mode: 512 Kbytes The user boot memory MAT is initiated at a power-on reset in user boot mode: 8 Kbytes * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. * Programming/erasing time The flash memory programming time is 3 ms (typ) in 128-byte simultaneous programming, and approximately 25 s per byte. The erasing time is 1000 ms (typ) per 64-Kbyte block. * Number of programming The number of flash memory programming can be up to 100 times at the minimum. (The value ranged from 1 to 100 is guaranteed.) * Three on-board programming modes Boot mode This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. In this mode, the bit rate between the host and this LSI can be automatically adjusted. User program mode The user MAT can be programmed by using the optional interface. Rev. 1.00 Sep. 21, 2006 Page 457 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) User boot mode The user boot program of the optional interface can be made and the user MAT can be programmed. * Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. * Programmer mode This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed. Internal address bus Internal data bus (16 bits) FCCS FPCS Module bus FECS FKEY FMATS FTDAR Control unit Memory MAT unit User MAT: 512 Kbytes User boot MAT: 8 Kbytes Flash memory Mode pins Operating mode [Legend] FCCS: Flash code control status register FPCS: Flash program code select register FECS: Flash erase code select register FKEY: Flash key code register FMATS: Flash MAT select register FTDAR: Flash transfer destination address register Note: To read from or write to the registers, the FLSHE bit in the serial timer control register (STCR) must be set to 1. Figure 19.1 Block Diagram of Flash Memory Rev. 1.00 Sep. 21, 2006 Page 458 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.1.1 Mode Transitions When each mode pin is set in the reset state and the reset is started, this LSI enters each operating mode as shown in figure 19.2. 1. Flash memory can be read in user mode, but cannot be programmed or erased. 2. Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. 3. Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode. RES = 0 Reset state Programmer mode setting Programmer mode =0 S RE Us er =0 m od es in ett g Bo RE ot mo de S =0 ot g bo tin er set Us de mo RE S RES se ttin g =0 FLSHE = 0 User mode FLSHE = 1 User program mode User boot mode On-board programming mode Boot mode Figure 19.2 Mode Transition for Flash Memory Rev. 1.00 Sep. 21, 2006 Page 459 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 19.1. Table 19.1 Comparison of Programming Modes Boot Mode Programming/ erasing environment Programming/ erasing enable MAT All erasure Block division erasure Program data transfer Reset initiation MAT Transition to user mode On-board User Program Mode On-board User Boot Mode On-board Programmer Mode PROM programmer User MAT User boot MAT (Automatic) User MAT User boot MAT (Automatic) * 1 User MAT User MAT x From host via SCI Via optional device Via optional device Via programmer Embedded program storage MAT Changing mode setting and reset User MAT User boot MAT*2 Changing FLSHE bit setting Changing mode setting and reset Notes: 1. All erasure is performed. After that, the specified block can be erased. 2. First, the reset vector is fetched from the embedded program storage MAT. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT. * The user boot MAT can be programmed or erased only in boot mode and programmer mode. * In boot mode, the user MAT and user boot MAT are totally erased. Then, the user MAT or user boot MAT can be programmed by means of commands. Note that the contents of the MAT cannot be read until this state. Boot mode can be used for programming only the user boot MAT and then programming the user MAT in user boot mode. Another way is to program only the user MAT since user boot mode is not used. * In user boot mode, boot operation of the optional interface can be performed with mode pin settings different from those in user program mode. Rev. 1.00 Sep. 21, 2006 Page 460 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.1.3 Flash Memory MAT Configuration This LSI's flash memory is configured by the 512-Kbyte user MAT and 8-Kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed only in boot mode and programmer mode. 512 Kbytes Address H'07FFFF Figure 19.3 Flash Memory Configuration The size of the user MAT is different from that of the user boot MAT. An address that exceeds the size of the 8-Kbyte user boot MAT should not be accessed. If the attempt is made, data is read as an undefined value. 19.1.4 Block Division The user MAT is divided into 64 Kbytes (seven blocks), 32 Kbytes (one block), and 4 Kbytes (eight blocks) as shown in figure 19.4. The user MAT can be erased in this divided-block units by specifying the erase-block number of EB0 to EB15 when erasing. Rev. 1.00 Sep. 21, 2006 Page 461 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) H'000000 H'000F80 H'000001 H'000F81 H'001001 H'000002 H'000F82 H'001002 EB1 Erase unit: 4 Kbytes H'001000 H'001F80 EB2 Erase unit: 4 Kbytes H'002000 H'001F81 H'002001 H'001F82 H'002002 H'002F80 EB3 Erase unit: 4 Kbytes H'003000 H'002F81 H'003001 H'002F82 H'003002 H'003F80 EB4 Erase unit: 32 Kbytes H'004000 H'003F81 H'004001 H'003F82 H'004002 H'00BF82 H'00C002 H'00CF82 H'00D002 H'00DF82 H'00E002 H'00EF82 H'00BF80 H'00BF81 EB5 Erase unit: 4 Kbytes H'00C000 H'00C001 H'00CF80 H'00CF81 EB6 Erase unit: 4 Kbytes H'00D000 H'00D001 H'00DF80 H'00DF81 EB7 Erase unit: 4 Kbytes H'00E000 H'00E001 H'00EF80 H'00EF81 EB8 Erase unit: 4 Kbytes H'00F000 H'00F001 H'00F002 H'00FF80 H'00FF81 EB9 Erase unit: 64 Kbytes H'010000 H'010001 H'00FF82 H'010002 H'01FF82 H'020002 H'01FF80 H'01FF81 EB10 Erase unit: 64 Kbytes H'020000 H'020001 H'02FF80 H'02FF81 EB11 Erase unit: 64 Kbytes H'030000 H'030001 H'02FF82 H'030002 H'03FF82 H'03FF80 H'03FF81 Figure 19.4 Block Division of User MAT (1) Rev. 1.00 Sep. 21, 2006 Page 462 of 658 REJ09B0310-0100 EB0 Erase unit: 4 Kbytes Programming unit: 128 bytes H'00007F H'000FFF H'00107F H'001FFF H'00207F Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes H'002FFF H'00307F H'003FFF H'00407F H'00BFFF H'00C07F H'00CFFF H'00D07F H'00DFFF H'00E07F Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes H'00EFFF H'00F07F H'00FFFF H'01007F Programming unit: 128 bytes Programming unit: 128 bytes H'01FFFF H'02007F H'02FFFF H'03007F Programming unit: 128 bytes H'03FFFF Section 19 Flash Memory (0.18-m F-ZTAT Version) EB12 Erase unit: 64 Kbytes H'040000 H'040001 H'040002 H'04FF82 H'050002 Programming unit: 128 bytes H'04FF80 H'04FF81 EB13 Erase unit: 64 Kbytes H'050000 H'050001 H'05FF80 H'05FF81 EB14 Erase unit: 64 Kbytes H'060000 H'060001 H'05FF82 H'060002 H'06FF80 H'06FF81 EB15 Erase unit: 64 Kbytes H'070000 H'070001 H'06FF82 H'070002 H'07FF80 H'07FF81 H'07FF82 Figure 19.4 Block Division of User MAT (2) H'04007F H'04FFFF H'05007F H'05FFFF H'06007F Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes H'06FFFF H'07007F H'07FFFF Rev. 1.00 Sep. 21, 2006 Page 463 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 19.4.2, User Program Mode. Start user procedure program for programming/erasing Select on-chip program to be downloaded and specify the destination Download on-chip program by setting the FKEY and SCO bits Initialization execution (downloaded program execution) Programming (in 128-byte units) or erasing (in one-block units) (downloaded program execution) No Programming/erasing completed? Yes End user procedure program Figure 19.5 Overview of User Procedure Program Rev. 1.00 Sep. 21, 2006 Page 464 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 1. Selection of on-chip program to be downloaded For programming/erasing execution, set the FLSHE bit in STCR to 1 to make a transition to user program mode. This LSI has programming/erasing programs that can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface register. The address of the download destination is specified by the flash transfer destination address register (FTDAR). 2. Download of on-chip program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control status register (FCCS), which are programming/erasing interface registers. The flash memory MAT is replaced with the embedded program storage MAT during downloading. Since the flash memory cannot be read during programming/erasing, the procedure program that executes download to completion of programming/erasing must be executed in a space other than flash memory (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameter, whether download has succeeded or not can be confirmed. 3. Initialization of programming/erasing Set the operating frequency before execution of programming/erasing. This setting is performed by using the programming/erasing interface parameter. 4. Execution of programming/erasing For programming/erasing execution, set the FLSHE bit in STCR to 1 to make a transition to user program mode. The program data/programming destination address is specified in 128-byte units for programming. The block to be erased is specified in erase-block units for erasing. Make these specifications by using the programming/erasing interface parameter, and then initiate the on-chip program. The on-chip program is executed by using the JSR or BSR instruction to execute the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts must be disabled during programming and erasing. Interrupts must be masked within the user system. Rev. 1.00 Sep. 21, 2006 Page 465 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 5. Consecutive execution of programming/erasing When the 128-byte programming or one-block erasure does not end the processing, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program remains in the on-chip RAM even after the processing ends, download and initialization are not required when the same processing is executed consecutively. 19.2 Input/Output Pins Flash memory is controlled by the pins listed in table 19.2. Table 19.2 Pin Configuration Pin Name RES MD2* MD1 MD0 TxD1 RxD1 Note: * Input/Output Input Input Input Input Output Input Function Reset Sets operating mode of this LSI Sets operating mode of this LSI Sets operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode) MD2 is not supported in SDIP-64 and QFP-64. Rev. 1.00 Sep. 21, 2006 Page 466 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.3 Register Descriptions The registers/parameters that control flash memory are shown below. To read from or write to these registers/parameters, the FLSHE bit in STCR must be set to 1. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * * * * * * * * * * * * Flash code control status register (FCCS) Flash program code select register (FPCS) Flash erase code select register (FECS) Flash key code register (FKEY) Flash MAT select register (FMATS) Flash transfer destination address register (FTDAR) Download pass/fail result (DPFR) Flash pass/fail result (FPFR) Flash multipurpose address area (FMPAR) Flash multipurpose data destination area (FMPDR) Flash erase block select (FEBS) Flash programming/erasing frequency control (FPEFEQ) There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence between operating modes and registers/parameters for use is shown in table 19.3. Rev. 1.00 Sep. 21, 2006 Page 467 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.3 Register/Parameter and Target Mode Download Initialization Programming/ FCCS erasing interface FPCS registers FECS FKEY FMATS FTDAR Programming/ DPFR erasing interface FPFR parameters FPEFEQ FMPAR FMPDR FEBS Programming * 1 Erasure * 1 Read *2 Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT. 19.3.1 Programming/Erasing Interface Registers The programming/erasing interface registers are all 8-bit registers that can be accessed in bytes. These registers are initialized at a reset or in hardware standby mode. * Flash Code Control Status Register (FCCS) FCCS requests monitoring error occurrence during programming or erasing flash memory, and the download of an on-chip program. Bit 7 6 5 Initial Bit Name Value FWE 1 0 0 R/W R R/W R/W Description Flash Write Enable This bit is always read as 1 and cannot be modified. Reserved The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 468 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Bit 4 Initial Bit Name Value FLER 0 R/W R Description Flash Memory Error Indicates an error has occurred during programming or erasing flash memory. When this bit is set to 1, flash memory enters the error-protection state. In case this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset must be released after a reset period of 100 s which is longer than normal. 0: Flash memory operates normally. Programming/erasing protection (error protection) for flash memory is invalid. [Clearing condition] * At a reset or in hardware standby mode 1: An error occurs during programming/erasing flash memory. Programming/erasing protection (error protection) for flash memory is valid. [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasing flash memory. When flash memory is read during programming/erasing flash memory (including a vector read or an instruction fetch). When the SLEEP instruction is executed during programming/erasing flash memory (including software standby mode) When a bus master other than the CPU, such as the DTC or LPC, gets bus mastership during programming/erasing flash memory. * * 3 to 1 All 0 R/W Reserved The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 469 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Bit 0 Initial Bit Name Value SCO 0 R/W (R)/W* Description Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR. In order to set this bit to 1, H'A5 must be written to FKEY and this operation must be executed in the on-chip RAM. Immediately after setting this bit to 1, four NOP instructions must be executed. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. All interrupts must be disabled during downloading. Interrupts must be masked within the user system. 0: Download of the on-chip programming/erasing program to the on-chip RAM is not executed. [Clearing condition] When download is completed 1: Request to download the on-chip programming/erasing program to the on-chip RAM has occurred. [Setting conditions] When all of the following conditions are satisfied and this bit is set to 1 * H'A5 is written to FKEY * During execution in the on-chip RAM Note: * This bit is a write only bit. This bit is always read as 0. Rev. 1.00 Sep. 21, 2006 Page 470 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit 7 to 1 0 Initial Bit Name Value PPVS All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Program Pulse Verify Selects the programming program. 0: On-chip programming program is not selected. [Clearing condition] When transfer is completed 1: On-chip programming program is selected. * Flash Erase Code Select Register (FECS) FECS selects the on-chip erasing program to be downloaded. Bit 7 to 1 0 Initial Bit Name Value EPVB All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected. [Clearing condition] When transfer is completed 1: On-chip erasing program is selected. Rev. 1.00 Sep. 21, 2006 Page 471 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * Flash Key Code Register (FKEY) FKEY is for software protection that enables download of an on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 to download an on-chip program or before executing the downloaded programming/erasing program, the key code must be written, otherwise the processing cannot be executed. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Key Code Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be set to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing can be executed. Even if the on-chip programming/erasing program is executed, the flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set by a value other than H'A5.) H'5A: Programming/erasing is enabled. (Software protection state is entered for a value other than H'5A.) H'00: Initial value Rev. 1.00 Sep. 21, 2006 Page 472 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description MAT Select The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected when H'AA is written. The MAT is switched by writing a value in FMATS. When the MAT is switched, follow section 19.6, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user program mode even if the user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or programmer mode.) H'AA: User boot MAT is selected (user MAT is selected when the value of these bits is other than H'AA). Initial value when initiated in user boot mode. H'00: Initial value when initiated in a mode except for user boot mode (user MAT is selected) [Programmable condition] In the execution state in the on-chip RAM Note: * Set to 1 in user boot mode, otherwise cleared to 0. Rev. 1.00 Sep. 21, 2006 Page 473 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address where an on-chip program is downloaded. This register must be specified before setting the SCO bit in FCCS to 1. Bit 7 Initial Bit Name Value TDER 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address where an onchip program is downloaded, is over the range. Whether or not the address specified by bits TDA6 to TDA0 is within the range of H'00 to H'02 is determined when an on-chip program is downloaded by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 and the value specified by bits TDA6 to TDA0 is within the range of H'00 to H'02 before setting the SCO bit to 1. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is outside the range (H'03 to H'7F) and download is stopped. 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address Specifies the start address where an on-chip program is downloaded. A value of H'00 can be specified as the download start address in the on-chip RAM. H'00: H'FFD080 is specified as the download start address. H'01: H'FFD880 is specified as the download start address. H'02: H'FFE080 is specified as the download start address. H'03 to H'7F: Setting prohibited. Specifying this value sets the TDER bit to 1 during downloading and stops the download. Rev. 1.00 Sep. 21, 2006 Page 474 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.3.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. These parameters use the CPU general registers (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a reset or in hardware standby mode. In download, initialization, or execution of the on-chip program, registers of the CPU except for R0L are stored. The return value of the processing result is written in R0L. Since the stack area is used for storing the registers except for R0L, the stack area must be saved at the processing start. (A maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters is used for the following four functions: 1. 2. 3. 4. Download control Initialization before programming or erasing Programming Erasing These items use different parameters. The correspondence table is shown in table 19.4. The meaning of bits in FPFR varies in each processing: initialization, programming, or erasure. For details, see descriptions of FPFR for each processing. Rev. 1.00 Sep. 21, 2006 Page 475 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.4 Parameters and Target Modes Abbrevia- Download Parameter Name tion Download pass/fail result Flash pass/fail result DPFR FPFR Initialization Programming Erasure R/W R/W R/W R/W Initial Value Allocation Undefined On-chip RAM* Undefined R0L of CPU Undefined ER0 of CPU FPEFEQ Flash programming/ erasing frequency control Flash multipurpose address area FMPAR R/W Undefined ER1 of CPU FMPDR Flash multipurpose data destination area Flash erase block select FEBS R/W Undefined ER0 of CPU R/W Undefined R0L of CPU Note: * A single byte of the download start address specified by FTDAR. (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area where the program is to be downloaded is the 2-Kbyte area starting from the address specified by FTDAR. Download control is set by the programming/erasing interface registers, and the DPFR parameter indicates the return value. (a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading was executed or not. Since confirmation whether the SCO bit is set to 1 or not is difficult, certain determination must be gained by setting a value other than the return value of download (for example, H'FF) to the single byte of the start address specified by FTDAR before download starts (before setting the SCO bit to 1). Rev. 1.00 Sep. 21, 2006 Page 476 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Bit 7 to 3 2 Initial Bit Name Value SS R/W R/W Description Unused The return value is 0. Source Select Error Detect Only one type can be specified for the on-chip program that can be downloaded. When more than two types of programs are selected, the program is not selected, or the program is selected without mapping, an error occurs. 0: Download program selection is normal 1: Download error has occurred (multi-selection or program which is not mapped is selected) 1 FK R/W Flash Key Register Error Detect Returns the check result whether the FKEY value is set to H'A5. 0: FKEY setting is normal (FKEY = H'A5) 1: FKEY setting is abnormal (FKEY = value other than H'A5) 0 SF R/W Success/Fail Returns the result whether download has ended normally or not. Determines the result whether the program was correctly downloaded to the on-chip RAM by way of the confirming reading of it. 0: Download to on-chip program has ended normally (no error) 1: Download to on-chip program has ended abnormally (error occurred) Rev. 1.00 Sep. 21, 2006 Page 477 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. A pulse of the specified width must be applied when programming or erasing. The specified pulse width is made by the method in which a wait loop is configured by CPU instructions. The operating frequency of the CPU must be set too. The initialization program is used to set the above values as parameters of the programming/erasing program that was downloaded. (a) Flash programming/erasing frequency control parameter (FPEFEQ: general register ER0 of CPU) This parameter sets the operating frequency of the CPU. The settable range of the operating frequency in this LSI is 8 to 20 MHz. Bit Initial Bit Name Value R/W R/W Description Unused These bits should be cleared to 0. 15 to 0 F15 to F0 Frequency Set These bits set the operating frequency of the CPU. The setting value must be calculated with the following procedure. 1. The operating frequency shown in MHz units must be rounded off to two decimals. 2. The value multiplied by 100 is converted to the hexadecimal numeral and written to the FPEFEQ parameter (general register ER0). For example, when the operating frequency of the CPU is 20.000 MHz, the setting value is as follows: 1. 20.000 is rounded off to two decimals, thus becoming 20.00. 2. The formula of 20.00 x 100 = 2000 is converted to the hexadecimal numeral and H'07D0 is set to ER0. 31 to 16 Rev. 1.00 Sep. 21, 2006 Page 478 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (b) Flash pass/fail result parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the initialization result. Bit 7 to 2 1 Initial Bit Name Value FQ R/W R/W Description Unused The return value is 0. Frequency Error Detect Returns the check result whether the specified CPU operating frequency is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Indicates whether initialization has ended normally or not. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurred) (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data has been downloaded. 1. The start address of the programming destination on the user MAT must be set in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). Since the program data is always in 128-byte units, the lower eight bits (A7 to A0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in a consecutive area. The program data must be in the consecutive space that can be accessed by using the MOV.B instruction of the CPU and in an address space other than flash memory. When data to be programmed does not satisfy 128 bytes, 128-byte program data must be prepared by filling in the dummy code H'FF. The start address of the area in which the prepared program data is stored must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). Rev. 1.00 Sep. 21, 2006 Page 479 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) For details on the programming procedure, see section 19.4.2, User Program Mode. (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter stores the start address of the programming destination on the user MAT. When the address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in the FPFR parameter. Bit Initial Bit Name Value R/W R/W Description These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified programming start address becomes a 128-byte boundary and the MOA6 to MOA0 bits are always 0. 31 to 0 MOA31 to MOA0 (b) Flash multipurpose data destination area parameter (FMPDR: general register ER0 of CPU) This parameter stores the start address of the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in the FPFR parameter. Bit Initial Bit Name Value R/W R/W Description These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address. 31 to 0 MOD31 to MOD0 Rev. 1.00 Sep. 21, 2006 Page 480 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (c) Flash pass/fail result parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the programming processing result. Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused The return value is 0. Programming Mode Related Setting Error Detect Returns the check result of the error-protection state not being entered. When a low-level signal is input to the FWE pin or the error-protection state is entered, 1 is written to this bit. These states can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error-protection state, see section 19.5.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: Programming cannot be performed because FWE = 0 or FLER = 1 5 EE R/W Programming Execution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally and programming result is not guaranteed Rev. 1.00 Sep. 21, 2006 Page 481 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Bit 4 Initial Bit Name Value FK R/W R/W Description Flash Key Register Error Detect Returns the check result of the FKEY value before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is abnormal (FKEY = value other than H'5A) 3 2 WD R/W Unused The return value is 0. Write Data Address Detect When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of program data address is normal 1: Setting of program data address is abnormal 1 WA R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * * When the specified programming destination address is in an area other than flash memory When the specified address is not at a 128-byte boundary (the lower eight bits of the address are other than H'00 or H'80) 0: Setting of programming destination address is normal 1: Setting of programming destination address is abnormal 0 SF R/W Success/Fail Indicates whether the programming processing has ended normally or not. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurred) Rev. 1.00 Sep. 21, 2006 Page 482 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program that is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block numbers 0 to 23. For details on the erasing procedure, see section 19.4.2, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be selected at one time. Bit Initial Bit Name Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Unused These bits should be cleared to 0. 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Erase Block These bits set the erase-block number in the range from 0 to 15. 0 corresponds to the EB0 block and 15 corresponds to the EB15 block. An error occurs when a number other than 0 to 15 (H'00 to H'0F) is set. 31 to 8 Rev. 1.00 Sep. 21, 2006 Page 483 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (b) Flash pass/fail result parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the erasing processing result. Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused The return value is 0. Erasing Mode Related Setting Error Detect Returns the check result of the error-protection state not being entered. When the error-protection state is entered, 1 is written to this bit. This state can be confirmed with the FLER bit in FCCS. For conditions to enter the error-protection state, see section 19.5.3, Error Protection. 0: FLER setting is normal (FLER = 0) 1: Erasing cannot be performed because FLER = 1 5 EE R/W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally and erasure result is not guaranteed 4 FK R/W Flash Key Register Error Detect Returns the check result of the FKEY value before the start of the erasing processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is abnormal (FKEY = value other than H'5A) Rev. 1.00 Sep. 21, 2006 Page 484 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Bit 3 Initial Bit Name Value EB R/W R/W Description Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal 2, 1 0 SF R/W Unused The return value is 0. Success/Fail Indicates whether the erasing processing has ended normally or not. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurred) Rev. 1.00 Sep. 21, 2006 Page 485 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.4 On-Board Programming When the pins are set to on-board programming mode and the reset start is executed, a transition is made to an on-board programming state in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user program mode, and user boot mode. For details on the pin setting for entering each mode, see table 19.5. For details of the state transition of each mode for flash memory, see figure 19.2. Table 19.5 On-Board Programming Mode Setting Mode Setting Boot mode User program mode* User boot mode 1 MD2*2 0 0 0 MD1 0 1 0 MD0 0 0/1 0 NMI 1 0/1 0 P42 1 1 P41 1 1 P40 1 1 Notes: 1. Before downloading a programming/erasing program, the FLSHE bit must be set to 1 to make a transition to user program mode. 2. MD2 is not supported in SDIP-64 and QFP-64. 19.4.1 Boot Mode Boot mode executes programming/erasing of the user MAT and user boot MAT by means of the control commands and program data transmitted from the host via the on-chip SCI. The tool for transmitting the control commands, and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pins have been set to boot mode, the boot program built in the microcomputer beforehand is initiated. After the SCI bit rate is automatically adjusted, communication with the host is executed by means of control commands. A system configuration diagram in boot mode is shown in figure 19.6. For details on the pin settings in boot mode, see table 19.5. The NMI and other interrupts are ignored in boot mode. However, the NMI and other interrupts should be disabled within the user system. Rev. 1.00 Sep. 21, 2006 Page 486 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) This LSI Analysis execution software (on-chip) Control command and program data Flash memory Host Boot programming tool and program data RxD1 On-chip SCI_1 TxD1 Reply response On-chip RAM Figure 19.6 System Configuration in Boot Mode (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI communication data (H'00) which is transmitted consecutively from the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and then transmits 1 byte of H'55 to this LSI. When reception has not been executed normally, boot mode is initiated again (reset) and the operation described above must be performed. The bit rates of the host and this LSI do not match due to the bit rate of transmission by the host and the system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 4,800 bps, 9,600 bps, or 19,200 bps. The system clock frequency, which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI, is shown in table 19.6. Boot mode must be initiated in the range of this system clock. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 19.7 Automatic-Bit-Rate Adjustment Operation of SCI Rev. 1.00 Sep. 21, 2006 Page 487 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI Bit Rate of Host 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI 8 to 20 MHz 8 to 20 MHz 8 to 20 MHz (2) State Transition Diagram The overview of the state transition diagram after boot mode is initiated is shown in figure 19.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about the user MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MATs and user boot MATs After inquiries have finished, all user MATs and user boot MATs are automatically erased. 4. Waiting for programming/erasing command When the program preparation notice is received, the state for waiting for program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state of program data wait is returned to the state of programming/erasing command wait. When the erasure preparation notice is received, the state for waiting for erase-block data is entered. The erase-block number must be transmitted following the erasing command. When the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the state of erase-block data wait is returned to the state of programming/erasing command wait. This erasing operation should be used in a case where after programming has been executed in boot mode, a specific block is to be reprogrammed without a reset start. When programming can be executed by only one operation, since all blocks are erased before entering the state for waiting for a programming/erasing/other command, the erasing operation is not required. There are many commands other than programming/erasing. For example, sum check, blank check (erasure check), and memory read of the user MAT and user boot MAT, and acquisition of current status information. Note that memory read of the user MAT or user boot MAT can only read out the programmed data after all user MATs or user boot MATs have been automatically erased. Rev. 1.00 Sep. 21, 2006 Page 488 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (Bit rate adjustment) H'00, ..., H'00 reception Boot mode initiation (reset in boot mode) H'00 transmission (adjustment completed) ptio rece H'55 n Bit rate adjustment 1 Inquiry command reception 2 Wait for inquiry setting command Inquiry command response Processing of inquiry setting command 3 Erasure of all user MATs and all user boot MATs 4 Wait for programming/erasing command Read/check command reception Command response Processing of read/check command (Erasure end) (Erasure selection command reception) (Erase-block specification) (Programming end) (Programming selection command reception) (Program data transmission) Wait for erase-block data Wait for program data Figure 19.8 Overview of Boot Mode State Transition Diagram Rev. 1.00 Sep. 21, 2006 Page 489 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program built in the microcomputer beforehand. The programming/erasing overview flow is shown in figure 19.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, a transition to the reset state or hardware standby mode must not be made. Doing so may damage and destroy flash memory. If a reset is executed accidentally, the reset must be released after a reset input period of 100 s which is longer than normal. Programming/erasing start 1. Make sure the program data does not overlap the download destination specified by FTDAR. 2. Programming/erasing can be executed only in the on-chip RAM. When programming, program data is prepared Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 19.9 Programming/Erasing Overview Flow Rev. 1.00 Sep. 21, 2006 Page 490 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (1) On-Chip RAM Address Map when Programming/Erasing is Executed Part of the procedure program that is made by the user, like the download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that areas in the on-chip RAM must be controlled so that these parts do not overlap. Figure 19.10 shows the area where a program is downloaded. Note: * Differs according to the area specified by FTDAR since the on-chip RAM area in this LSI is split into H'FFD080 to H'FFEFFF and H'FFFF00 to H'FFFF7F. Figure 19.10 RAM Map when Programming/Erasing is Executed Rev. 1.00 Sep. 21, 2006 Page 491 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 19.11. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 (a) (b) Programming Disable interrupts and bus master operation other than CPU Set FKEY to H'5A (i) (j) (k) (l) (m) No Download Set SCO to 1 and execute download (c) (d) No Set the parameters to ER1 and ER0 (FMPAR, FMPDR) Programming JSR FTDAR setting + 16 FPFR = 0? Clear FKEY to 0 DPFR = 0? (e) Yes Set the FPEFEQ parameter Download error processing Yes No Required block programming is completed? Clear FKEY Programming error processing (f) (g) (h) Initialization (n) (o) Initialization JSR FTDAR setting + 32 FPFR = 0 ? Yes Clear FKEY to 0 End programming procedure program No Yes Initialization error processing 1 Figure 19.11 Programming Procedure The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 19.4.4, Storable Areas for Procedure Program and Program Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been done yet, execute erasing before writing. Rev. 1.00 Sep. 21, 2006 Page 492 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 128-byte programming is performed in one programming processing. To program more than 128 bytes, update the programming destination address/program data parameter in 128-byte units and repeat programming. When less than 128 bytes of programming is performed, the program data must amount to 128 bytes by filling in invalid data. If the invalid data to be added is H'FF, the programming processing time can be shortened. (a) Select the on-chip program to be downloaded and specify a download destination When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the SS bit in DPFR. The start address of the download destination is specified by FTDAR. (b) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be set to the SCO bit for a download request. (c) Set the SCO bit in FCCS to 1 to execute download. To set 1 to the SCO bit, the following conditions must be satisfied. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is already cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of DPFR. To prevent incorrect determination, before the SCO bit is set to 1, set the single byte of the on-chip RAM start address (to be used as the DPFR parameter) specified by FTDAR to a value (e.g. H'FF) other than the return value. When download is executed, particular interrupt processing, which is accompanied by bank switchover as described below, is performed as a microcomputer internal processing. Execute four NOP instructions immediately after the instruction that sets the SCO bit to 1. Rev. 1.00 Sep. 21, 2006 Page 493 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * The user MAT space is switched to the embedded program storage MAT. * After the selection condition of the download program and the FTDAR address setting are checked, the transfer processing to the on-chip RAM specified by FTDAR is executed. * The SCO bit in FPCS, FECS, and FCCS is cleared to 0. * The return value is set to the DPFR parameter. * After the embedded program storage MAT is returned to the user MAT space, execution returns to the user procedure program. * In the download processing, the values of CPU general registers are retained. * In the download processing, all interrupts are not accepted. However, interrupt requests except for NMI are held. Therefore, when execution returns to the user procedure program, the interrupts will occur. * When the level-detection interrupt requests are to be held, interrupts must be input until the download is ended. * When hardware standby mode is entered during the download processing, normal download to the on-chip RAM cannot be guaranteed. Therefore, download must be executed again. * Since a stack area of 128 bytes at the maximum is used, the stack area must be allocated before setting the SCO bit to 1. * If a flash memory access by the DTC is requested during downloading, the operation cannot be guaranteed. Therefore, access by the DTC must not occur. (d) (e) Clear FKEY to H'00 for protection. Check the value of the DPFR parameter to confirm the download result. * Check the value of the DPFR parameter (single byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit and FK bit in the DPFR parameter to ensure that the download program selection and FKEY setting were normal, respectively. Rev. 1.00 Sep. 21, 2006 Page 494 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (f) Set the operating frequency to the FPEFEQ parameter for initialization. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register ER0). The settable range of the FPEFEQ parameter is 8 to 20 MHz. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in section 19.3.2 (2) (a), Flash programming/erasing frequency control parameter (FPEFEQ: general register ER0 of CPU). (g) Initialization When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point for the initialization program in the area from the start address of a download destination specified by FTDAR + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L JSR NOP #DLTOP+32,ER2 @ER2 ; Set entry address to ER2 ; Call initialization routine * The general registers other than R0L are saved in the initialization program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the initialization program, a 128-byte stack area at the maximum must be allocated in RAM. * Interrupts can be accepted during the execution of the initialization program. Note however that the program storage area and stack area in the on-chip RAM, and register values must not be rewritten. (h) The return value in the initialization program, FPFR (general register R0L) is determined. All interrupts and the use of a bus master other than the CPU are prohibited. (i) The stipulated voltage is applied for the stipulated time when programming or erasing. If interrupts occur or a bus master other than the CPU gets the bus during this period, a voltage pulse exceeding the specification may be applied, thus damaging flash memory. Accordingly, interrupts must be disabled and a bus master other than the CPU, such as the DTC, must not be allowed. To disable interrupts, bit 7 (I) in the condition code register (CCR) of the CPU should be set to B'1 in interrupt control mode 0, or bits 7 and 6 (I and UI) in the condition code register (CCR) of the CPU should be set to B'11 in interrupt control mode 1. This enables interrupts other than NMI to be held and not executed. Rev. 1.00 Sep. 21, 2006 Page 495 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) The NMI interrupt must be masked within the user system. The interrupts that are held must be executed after all programming processings. When a bus master other than the CPU, such as the DTC, acquires the bus, the error-protection state is entered. Therefore, acquisition of the bus by the DTC must also be prohibited. (j) (k) Set H'5A in FKEY and prepare the user MAT for programming. Set the parameters required for programming. The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1, and the start address of the program data area (FMPDR) is set to general register ER0. * Example of FMPAR setting FMPAR specifies the programming destination address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the programming unit is 128 bytes, the lower eight bits of the address must be at the 128-byte boundary of H'00 or H'80. * Example of FMPDR setting When the storage destination of the program data is flash memory, even if the programming execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM before programming is executed. Rev. 1.00 Sep. 21, 2006 Page 496 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (l) Programming There is an entry point for the programming program in the area from the start address of a download destination specified by FTDAR + 16 bytes. The subroutine is called and programming is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine * The general registers other than R0L are saved in the programming program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the programming program, a 128-byte stack area at the maximum must be allocated in RAM. (m) The return value in the programming program, FPFR (general register R0L) is determined. (n) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128-byte units, and repeat steps (l) to (n). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address that has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (o) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) of 100 s which is longer than normal. Rev. 1.00 Sep. 21, 2006 Page 497 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 19.12. Start erasing procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR (a) Disable interrupts and bus master operation other than CPU Set FKEY to H'5A Set FKEY to H'A5 Download Set SCO to 1 and execute download Set the FEBS parameter Erasing JSR FTDAR setting + 16 (b) (c) (d) No Erasing Clear FKEY to 0 DPFR = 0? No Download error processing FPFR = 0? Yes Set the FPEFEQ parameter Yes No Required block erasing is completed? Clear FKEY Erasing error processing Initialization (e) (f) Initialization JSR FTDAR setting + 32 Yes Clear FKEY to 0 FPFR = 0 ? No Yes Initialization error processing End erasing procedure program 1 Figure 19.12 Erasing Procedure The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 19.4.4, Storable Areas for Procedure Program and Program Data. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 19.10. Rev. 1.00 Sep. 21, 2006 Page 498 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) A single divided block is erased by one erasing processing. For block divisions, refer to figure 19.4. To erase two or more blocks, update the erase-block number and perform the erasing processing for each block. (a) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is reported to the SS bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see section 19.4.2 (2), Programming Procedure in User Program Mode. The procedures after setting parameters for erasing programs are as follows: (b) Set the FEBS parameter necessary for erasure Set the erase-block number of the user MAT in the flash erase block select parameter FEBS (general register ER0). If a value other than an erase-block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (c) Erasure Similar to as in programming, there is an entry point for the erasing program in the area from the start address of a download destination specified by FTDAR + 16 bytes. The subroutine is called and erasing is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call erasing routine * The general registers other than R0L are saved in the erasing program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the erasing program, a 128-byte stack area at the maximum must be allocated in RAM. Rev. 1.00 Sep. 21, 2006 Page 499 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (d) (e) The return value in the erasing program, FPFR (general register R0L) is determined. Determine whether erasure of the necessary blocks has completed. If more than one block is to be erased, update the FEBS parameter and repeat steps (b) to (e). Blocks that have already been erased can be erased again. (f) After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after user MAT erasure has completed, secure a reset period (period of RES = 0) of 100 s which is longer than normal. (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 19.13 shows a repeating procedure of erasing and programming. Start procedure program Specify a download destination for erasing program by FTDAR Erasing program download 1 Erasing/ Programming Erase relevant block (execute erasing program) Set FMPDR to program relevant block (execute programming program) Download erasing program Initialize erasing program Programming program download Specify a download destination for programming program by FTDAR Download programming program Initialize programming program Confirm operation End ? No Yes 1 End procedure program Figure 19.13 Repeating Procedure of Erasing and Programming Rev. 1.00 Sep. 21, 2006 Page 500 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) In the above procedure, download and initialization are performed only once at the beginning. In this kind of operation, note the following: * Be careful not to damage on-chip RAM with overlapped settings. In addition to the erasing program area and programming program area, areas for the user procedure programs, work area, and stack area are allocated in the on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ parameter must be performed for both the erasing program and programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes and (download start address for programming program) + 32 bytes. 19.4.3 User Boot Mode This LSI has user boot mode that is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 19.5. When the reset start is executed in user boot mode, the built-in check routine runs. The user MAT and user boot MAT states are checked by this check routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to FMATS because the execution target MAT is the user boot MAT. Rev. 1.00 Sep. 21, 2006 Page 501 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (2) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 19.14 shows the procedure for programming the user MAT in user boot mode. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR 1 Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'A5 User-boot-MAT selection state Download Set SCO to 1 and execute download Set FKEY to H'5A User-MAT selection state Clear FKEY to 0 DPFR = 0? Yes Set parameter to ER0 and ER1 (FMPAR and FMPDR) No Programming Programming JSR FTDAR setting + 16 FPFR = 0? Download error processing Initialization Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0? No Yes Clear FKEY and programming error processing* No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT End programming procedure program MAT switchover 1 User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 19.14 Procedure for Programming User MAT in User Boot Mode Rev. 1.00 Sep. 21, 2006 Page 502 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 19.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After the programming procedure completes, switch the MATs again to return to the first state. MAT switching is enabled by writing a specific value to FMATS. Note however that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 19.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 19.4.4, Storable Areas for Procedure Program and Program Data. Rev. 1.00 Sep. 21, 2006 Page 503 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 19.15 shows the procedure for erasing the user MAT in user boot mode. Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 MAT switchover Set FMATS to value other than H'AA to select user MAT User-boot-MAT selection state Download Set SCO to 1 and execute download Set FKEY to H'A5 User-MAT selection state Clear FKEY to 0 Set FEBS parameter Programming JSR FTDAR setting + 16 FPFR = 0? DPFR = 0? No Yes Download error processing Erasing Initialization Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0? Yes No No Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT End erasing procedure program MAT switchover 1 User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 19.15 Procedure for Erasing User MAT in User Boot Mode Rev. 1.00 Sep. 21, 2006 Page 504 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 19.15. MAT switching is enabled by writing a specific value to FMATS. Note however that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 19.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 19.4.4, Storable Areas for Procedure Program and Program Data. 19.4.4 Storable Areas for Procedure Program and Program Data In the descriptions in the previous section, the storable areas for the programming/erasing procedure programs and program data are assumed to be in the on-chip RAM. However, the procedure programs and program data can be stored in and executed from other areas, such as part of flash memory which is not to be programmed or erased. (1) Conditions that Apply to Programming/Erasing 1. The on-chip programming/erasing program is downloaded from the address in the on-chip RAM specified by FTDAR, therefore, this area is not available for use. 2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So, make sure that this area is allocated. 3. Download by setting the SCO bit to 1 will lead to switching of the MATs. Therefore, if this operation is used, it should be executed from the on-chip RAM. 4. The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been determined. The required procedure programs, NMI handling vector, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing of the flash memory starts. 5. Since flash memory is not accessible during programming/erasing processing, programs downloaded to the on-chip RAM are executed. The procedure programs that initiate programming/erasing processing, and execution areas for the NMI interrupt vector table and NMI interrupt handling program must be stored in on-chip RAM. Rev. 1.00 Sep. 21, 2006 Page 505 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 6. After programming/erasing, access to the flash memory is prohibited until FKEY is cleared. In case the LSI mode is changed to generate a reset on completion of a programming/erasing operation, a reset state (RES = 0) of 100 s or more must be secured. Transitions to the reset state or hardware standby mode are prohibited during programming/erasing operations. However, when the reset signal is accidentally input to the chip, the reset must be released after a reset period of 100 s that is longer than normal. 7. Switching of the MATs by FMATS should be required when programming/erasing of the user MAT is operated in user boot mode. The program that switches the MATs should be executed from the on-chip RAM. (For details, see section 19.6, Switching between User MAT and User Boot MAT.) Make sure you know which MAT is currently selected when switching them. 8. When the program data storable area indicated by the programming parameter FMPDR is in flash memory, an error will occur even when the program data stored is normal. Therefore, the program data should be temporarily transferred to the on-chip RAM to set an address other than flash memory in FMPDR. In consideration of these conditions, the following tables show areas where program data can be stored and executed for different combinations of operating mode, user MAT bank configuration, and processing type. Table 19.7 Executable MAT Initiated Mode Processing Programming Erasing Note: * User Program Mode Table 19.8 (1) Table 19.8 (2) Programming/Erasing is possible to the user MAT. User Boot Mode* Table 19.8 (3) Table 19.8 (4) Rev. 1.00 Sep. 21, 2006 Page 506 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.8 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program Storage MAT Item Storage area for program data Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Writing H'5A to FKEY Setting programming parameter On-chip RAM User MAT x* User MAT x x x x Rev. 1.00 Sep. 21, 2006 Page 507 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Storable/Executable Area Selected MAT Embedded Program Storage MAT Item Programming Determination of programming result Programming error processing FKEY clearing Note: * On-chip RAM User MAT x x x x User MAT Transferring the data to the on-chip RAM in advance enables this area to be used. Rev. 1.00 Sep. 21, 2006 Page 508 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.8 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program Storage MAT Item Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Writing H'5A to FKEY Setting erasure parameter Erasure Determination of erasure result Erasing error processing FKEY clearing On-chip RAM User MAT User MAT x x x x x x x x Rev. 1.00 Sep. 21, 2006 Page 509 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.8 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area On-chip RAM User Boot MAT x* 1 Selected MAT User Boot MAT Embedded Program Storage MAT Item Storage area for program data Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Switching MATs by FMATS Writing H'5A to FKEY User MAT x x x x x Rev. 1.00 Sep. 21, 2006 Page 510 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Storable/Executable Area On-chip RAM User Boot MAT x x x x*2 x x Selected MAT User Boot MAT Embedded Program Storage MAT Item Setting programming parameter Programming Determination of programming result Programming error processing FKEY clearing Switching MATs by FMATS User MAT Notes: 1. Transferring the data to the on-chip RAM in advance enables this area to be used. 2. Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 1.00 Sep. 21, 2006 Page 511 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.8 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area On-chip RAM User Boot MAT Selected MAT User Boot MAT Embedded Program Storage MAT Item Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Switching MATs by FMATS Writing H'5A to FKEY Setting erasure parameter User MAT x x x x x x Rev. 1.00 Sep. 21, 2006 Page 512 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Storable/Executable Area Selected MAT Embedded Program Storage MAT Item Erasure Determination of erasure result Erasing error processing FKEY clearing Switching MATs by FMATS Note: * On-chip RAM User Boot MAT x x x* x x User MAT User Boot MAT Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 1.00 Sep. 21, 2006 Page 513 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.5 Protection There are two kinds of flash memory programming/erasing protection: hardware and software protection. 19.5.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization are possible. However, even though a programming/erasing program is initiated, the user MAT cannot be programmed/erased, and a programming/erasing error is reported with the FPFR parameter. Table 19.9 Hardware Protection Function to be Protected Item Reset, standby protection Description * The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and hardware standby mode, and the programming/erasing protection state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has stabilized after the power is supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified by the AC characteristics. If a reset is input during programming or erasure, values in the flash memory are not guaranteed. In this case, execute erasure and then execute programming again. Download Programming/ Erasure * Rev. 1.00 Sep. 21, 2006 Page 514 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.5.2 Software Protection Software protection is set up by disabling download of on-chip programming/erasing programs or by means of a key code. Table 19.10 Software Protection Function to be Protected Item Protection by SCO bit Description * Download Programming/ Erasure The programming/erasing protection state is entered by clearing the SCO bit in FCCS to 0 to disable downloading of the programming/erasing programs. Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and programming/erasing. Protection by FKEY * 19.5.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer entering runaway during programming/erasing of the flash memory or operations that are not following the stipulated procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error-protection state is entered, and this aborts the programming or erasure. The FLER bit is set to 1 in the following conditions: 1. When an interrupt such as NMI occurs during programming/erasing. 2. When the flash memory is read during programming/erasing (including a vector read or an instruction fetch). 3. When a SLEEP instruction (including software-standby mode) is executed during programming/erasing. Rev. 1.00 Sep. 21, 2006 Page 515 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 4. When a bus master other than the CPU, such as the DTC, acquires the bus during programming/erasing Error protection is cancelled only by a reset or a transition to hardware-standby mode. Note that the reset should be released after a reset period of 100 s which is longer than normal. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state transition diagram in figure 19.16 shows transitions to and from the error-protection state. Program mode Erase mode RES = 0 or STBY = 0 or =0 ES Y = 0 RB ST Reset or hardware standby mode (Hardware protection) Read disabled Programming/erasing disabled FLER = 0 Read disabled Programming/erasing enabled E FLER = 0 (S rro oft r wa oc re cu sta rre nd d by ) Error occurred RES = 0 or STBY = 0 Programming/erasing interface registers are in the initial state. Error-protection state Read enabled Programming/erasing disabled FLER = 1 Software standby mode Error-protection state (Software standby) Read disabled Programming/erasing disabled FLER = 1 Software-standby mode canceled Programming/erasing interface registers are in the initial state. Figure 19.16 Transitions to Error-Protection State Rev. 1.00 Sep. 21, 2006 Page 516 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.6 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2. To ensure that switching has finished and access is made to the newly switched MAT, execute four NOP instructions in the same on-chip RAM immediately after writing to FMATS (this prevents access to the flash memory during MAT switching). 3. If an interrupt has occurred during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching between MATs. In addition, configure the system so that NMI interrupts do not occur during MAT switching. 4. After the MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt handling is to be the same before and after MAT switching, transfer the interrupt handling routines to the on-chip RAM and set the WEINTE bit in FCCS to place the interruptvector table in the on-chip RAM. 5. Memory sizes of the user MAT and user boot MAT are different. Do not access a user boot MAT in a space of 8 Kbytes or more. If access goes beyond the 8-Kbyte space, the values read are undefined. Figure 19.17 Switching between User MAT and User Boot MAT Rev. 1.00 Sep. 21, 2006 Page 517 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.7 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as another mode for programming/erasing of programs and data. In programmer mode, a general PROM programmer that supports Renesas microcomputers with 512-Kbyte flash memory as a device type*1 can be used to freely write programs to the on-chip ROM. Programming/erasing is possible on the user MAT and user boot MAT*2. Figure 19.18 shows a memory map in programmer mode. A status-polling system is adopted for operation in automatic programming, automatic erasure, and status-read modes. In status-read mode, details of the internal signals are output after execution of automatic programming or automatic erasure. In programmer mode, a 12-MHz clock signal must be input. Notes: 1. In this LSI, set the programming voltage of the PROM programmer to 3.3 V. 2. For the PROM programmer and the version of its program, see the instruction manuals for socket adapter. MCU mode H'000000 This LSI Programmer mode H'00000 On-chip ROM area H'07FFFF H'7FFFF Figure 19.18 Memory Map in Programmer Mode Rev. 1.00 Sep. 21, 2006 Page 518 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.8 Serial Communication Interface Specifications for Boot Mode The boot program initiated in boot mode performs transmission and reception with the host PC via the on-chip SCI. The serial communication interface specifications for the host and boot program are shown below. (1) Status The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and transition to the bit-rate-adjustment state. The boot program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the boot program enters the inquiry/selection state. 2. Inquiry/Selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected in this state. After selection of these settings, the boot program makes a transition to the programming/erasing state by the command for a transition to the programming/erasing state. The boot program transfers the libraries required for erasure to the on-chip RAM and erases the user MATs and user boot MATs before the transition to the programming/erasing state. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum check and blank check are executed by sending commands from the host. The boot program states are shown in figure 19.19. Rev. 1.00 Sep. 21, 2006 Page 519 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Reset Bit-rate-adjustment state Inquiry/response wait Inquiry Inquiry and selection processing Response Response processing Transition to programming/erasing state Processing for erasing user MAT and user boot MAT Programming/erasing response wait Programming Programming processing Erasing Erasing processing Checking Check processing Figure 19.19 Boot Program States Rev. 1.00 Sep. 21, 2006 Page 520 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (2) Bit-Rate-Adjustment State The bit rate is adjusted by measuring the period of a low-level byte (H'00) transmitted from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state. The bit-rate-adjustment sequence is shown in figure 19.20. Host H'00 (30 times maximum) Boot Program Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Boot response) (H'FF (error)) Figure 19.20 Bit-Rate-Adjustment Sequence (3) Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. 1-byte commands and 1-byte responses These commands and responses are comprised of a single byte. They are the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. They are selection commands and responses to inquiries. The size of program data is not included under this heading because it is determined in another command. 3. Error response This response is an error response to the commands. It is two bytes of data, and consists of an error response and an error code. Rev. 1.00 Sep. 21, 2006 Page 521 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 4. Programming of 128 bytes The size is not specified in the commands. The data size is indicated in the response to the programming unit inquiry. 5. Memory read response This response consists of r4 bytes of data. 1-byte command or 1-byte response n-byte command or n-byte response Command or response Data Data size Command or response Checksum Error response Error code Error response 128-byte programming Address Command Data (n bytes) Checksum Memory read response Data size Response Data Checksum Figure 19.21 Communication Protocol Format * * * * * * * * * * Command (1 byte): Commands for inquiries, selection, programming, erasing, and checking Response (1 byte): Response to an inquiry Size (1 byte): The amount of transfer data excluding the command, size, and checksum Data (n bytes): Detailed data of a command or response Checksum (1 byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Error response (1 byte): Error response to a command Error code (1 byte): Type of the error Address (4 bytes): Address for programming Data (n bytes): Data to be programmed (n is indicated in the response to the programming unit inquiry.) Data size (4 bytes): Four-byte response to a memory read Rev. 1.00 Sep. 21, 2006 Page 522 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (4) Inquiry/Selection State The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed in table 19.11. Table 19.11 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported Device Inquiry Device Selection Clock Mode Inquiry Clock Mode Selection Division Ratio Inquiry Description Inquiry regarding device code and product name Selection of device code Inquiry regarding number of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of types of division ratios, and the number and values of each ratio type H'23 H'24 H'25 H'26 H'27 H'3F H'40 H'4F Operating Clock Frequency Inquiry Inquiry regarding the maximum and minimum values of the main clock and peripheral clock User Boot MAT Information Inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT User MAT Information Inquiry Erased Block Information Inquiry Programming Unit Inquiry New Bit Rate Selection Inquiry regarding the number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the size of program data Selection of the new bit rate Transition to Programming/Erasing Erasure of user MAT and user boot MAT, and State transition to programming/erasing state Boot Program Status Inquiry Inquiry into the processing status of the boot program The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be transmitted from the host in that order. These commands are needed in all cases. When two or more selection commands are transmitted at the same time, the last command will be valid. Rev. 1.00 Sep. 21, 2006 Page 523 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) All of these commands, except for boot program status inquiry (H'4F), will be valid until the boot program receives the programming/erasing state transition command (H'40). The host can choose the needed commands out of the above commands and make inquiries. The boot program status inquiry command (H'4F) remains valid even after the boot program has received the programming/erasing state transition command (H'40). (a) Supported Device Inquiry The boot program will return the device codes of the supported devices and the product names in response to the supported device inquiry command. Command H'20 * Command, H'20 (1 byte): Inquiry regarding supported devices Response H'30 Number of characters *** SUM Size Number of devices Product name Device code * Response, H'30 (1 byte): Response to the supported device inquiry * Size (1 byte): The number of bytes to be transferred, excluding the command, size, and checksum, that is, the total amount of data consisting the number of devices, the number of characters, device codes, and product names * Number of devices (1 byte): The number of device types supported by the boot program in the microcomputer * Number of characters (1 byte): The number of characters in the device codes and boot program's name * Device code (4 bytes): ASCII code of the supported product name * Product name (n bytes): ASCII code of the boot program type name * SUM (1 byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. Rev. 1.00 Sep. 21, 2006 Page 524 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (b) Device Selection The boot program will set the specified supported device in response to the device selection command. The program will return information on the selected device in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM * Command, H'10 (1 byte): Device selection * Size (1 byte): The number of characters in the device code. Fixed at 4. * Device code (4 bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (1 byte): Checksum Response H'06 * Response, H'06 (1 byte): Response to the device selection command. The boot program will return ACK when the device code matches. Error Response H'90 ERROR * Error response, H'90 (1 byte): Error response to the device selection command ERROR (1 byte): Error code H'11: Checksum error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry command. Command H'21 * Command, H'21 (1 byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode *** SUM * Response, H'31 (1 byte): Response to the clock mode inquiry * Size (1 byte): Amount of data that represents the number of modes and modes * Number of clock modes (1 byte): The number of supported clock modes. H'00 indicates no clock mode or the device allows the clock mode to be read. * Mode (1 byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (1 byte): Checksum Rev. 1.00 Sep. 21, 2006 Page 525 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode in response to the clock mode selection command. The program will return information on the selected clock mode in response to the inquiry after this setting has been made. The clock mode selection command should be sent after the device selection command. Command H'11 Size Mode SUM * * * * Command, H'11 (1 byte): Selection of clock mode Size (1 byte): The number of characters that represents the modes. Fixed at 1. Mode (1 byte): A clock mode returned in response to the clock mode inquiry. SUM (1 byte): Checksum H'06 Response * Response, H'06 (1 byte): Response to the clock mode selection command. The boot program will return ACK when the clock mode matches. Error Response H'91 ERROR * Error response, H'91 (1 byte): Error response to the clock mode selection command * ERROR (1 byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match Even if the number of clock modes is H'00 or H'01 by a clock mode inquiry, the clock mode must be selected using the respective value. Rev. 1.00 Sep. 21, 2006 Page 526 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (e) Division Ratio Inquiry The boot program will return the supported division ratios in response to the division ratio inquiry command. Command H'22 * Command, H'22 (1 byte): Inquiry regarding division ratio Response H'32 Number of division ratios *** SUM Size Division ratio Number of types *** * Response, H'32 (1 byte): Response to the division ratio inquiry * Size (1 byte): The amount of data that represents the number of types, number of division ratios, and division ratios * Number of types (1 byte): The number of supported division ratio types (e.g. H'02 when there are two types: main operating frequency and peripheral module operating frequency) * Number of division ratios (1 byte): The number of supported division ratios for each operating frequency. The number of division ratios supported in the main module and peripheral modules. * Division ratio (1 byte) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value will be H'FE[-2]) The number of division ratios returned is the same as the number of division ratios and as many groups of data are returned as there are types. * SUM (1 byte): Checksum Rev. 1.00 Sep. 21, 2006 Page 527 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values in response to the operating clock frequency inquiry command. Command H'23 * Command, H'23 (1 byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Minimum value of operating Maximum value of operating clock clock frequency frequency *** SUM * Response, H'33 (1 byte): Response to operating clock frequency inquiry * Size (1 byte): The amount of data that represents the number of operating clock frequencies, and the minimum and maximum values of the operating clock frequencies * Number of operating clock frequencies (1 byte): The number of supported operating clock frequency types (e.g. H'02 when there are two types: main operating frequency and peripheral module operating frequency) * Minimum value of operating clock frequency (2 bytes): Minimum value among the divided clock frequencies. The minimum and maximum values of operating clock frequency represent the frequency values (MHz), valid to the hundredths place, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0) * Maximum value of operating clock frequency (2 bytes): Maximum value among the divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (1 byte): Checksum Rev. 1.00 Sep. 21, 2006 Page 528 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses in response to the user boot MAT information inquiry command. Command H'24 * Command, H'24 (1 byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Area last address Area start address *** SUM * Response, H'34 (1 byte): Response to user boot MAT information inquiry * Size (1 byte): The amount of data that represents the number of areas, area start address, and area last address * Number of areas (1 byte): The number of consecutive user boot MAT areas. H'01 when the user boot MAT areas are consecutive. * Area start address (4 bytes): Start address of the area * Area last address (4 bytes): Last address of the area. There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses in response to the user MAT information inquiry command. Command H'25 * Command, H'25 (1 byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Area last address Area start address *** SUM * Response, H'35 (1 byte): Response to the user MAT information inquiry * Size (1 byte): The amount of data that represents the number of areas, area start address, and area last address * Number of areas (1 byte): The number of consecutive user MAT areas. H'01 when the user MAT areas are consecutive. Rev. 1.00 Sep. 21, 2006 Page 529 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * Area start address (4 bytes): Start address of the area * Area last address (4 bytes): Last address of the area. There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses in response to the erased block information inquiry command. Command H'26 * Command, H'26 (1 byte): Inquiry regarding erased block information Response H'36 Size Number of blocks Block last address Block start address *** SUM * Response, H'36 (1 byte): Response to the erased block information inquiry * Size (2 bytes): The amount of data that represents the number of blocks, block start address, and block last address. * Number of blocks (1 byte): The number of erased blocks of flash memory * Block start address (4 bytes): Start address of a block * Block last address (4 bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are blocks. * SUM (1 byte): Checksum (j) Programming Unit Inquiry The boot program will return the programming unit used to program data in response to the programming unit inquiry command. Command H'27 * Command, H'27 (1 byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM * Response, H'37 (1 byte): Response to programming unit inquiry * Size (1 byte): The number of characters that indicate the programming unit. Fixed at 2. * Programming unit (2 bytes): A unit for programming. This is the unit for reception of program data. Rev. 1.00 Sep. 21, 2006 Page 530 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * SUM (1 byte): Checksum (k) New Bit Rate Selection The boot program will set a new bit rate in response to the new bit rate selection command, and return the new bit rate in response to the confirmation. This new bit rate selection command should be sent after sending the clock mode selection command. Command H'3F Number of division ratios SUM Size Bit rate Input frequency Division ratio 1 Division ratio 2 * Command, H'3F (1 byte): Selection of new bit rate * Size (1 byte): The amount of data that represents the bit rate, input frequency, number of division ratios, and division ratios * Bit rate (2 bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (2 bytes): Frequency of the clock input to the boot program. This is valid to the hundredths place and represents the frequency value (MHz) multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0) * Number of division ratios (1 byte): The number of supported division ratios. Normally the number is two: one for the main operating frequency and one for peripheral module operating frequency. * Division ratio 1 (1 byte): The division ratio for the main operating frequency Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value will be H'FE[-2]) * Division ratio 2 (1 byte): The division ratio for the peripheral module operating frequency Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value will be H'FE[-2]) * SUM (1 byte): Checksum Response H'06 * Response, H'06 (1 byte): Response to selection of a new bit rate. The boot program will return ACK when the new bit rate can be set. Error Response H'BF ERROR * Error response, H'BF (1 byte): Error response to selection of a new bit rate Rev. 1.00 Sep. 21, 2006 Page 531 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) * ERROR (1 byte): Error code H'11: Checksum error H'24: Bit rate selection error The rate is not available. H'25: Input frequency error The input frequency is not within the specified range. H'26: Division ratio error The division ratio does not match an available ratio. H'27: Operating frequency error The operating frequency is not within the specified range. (5) Receive Data Check The methods for checking received data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of the minimum to maximum frequencies which are available with the clock modes of the specified device. When the value is out of this range, an input frequency error is generated. 2. Division ratio The received value of the division ratio is checked to ensure that it matches the division for the clock modes of the specified device. When the value is out of this range, a division ratio error is generated. 3. Operating frequency Operating frequency is calculated from the received value of the input frequency and the division ratio. The input frequency is the frequency input to the LSI, and the operating frequency is the frequency at which the LSI is actually operated. The formula is given below. Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of the minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate selection error is generated. The error is calculated using the following formula: Rev. 1.00 Sep. 21, 2006 Page 532 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 * Confirmation, H'06 (1 byte): Confirmation of a new bit rate Response H'06 * Response, H'06 (1 byte): Response to confirmation of a new bit rate The sequence of new bit rate selection is shown in figure 19.22. Host Setting a new bit rate Waiting for one-bit period at the specified bit rate Setting a new bit rate Boot program H'06 (ACK) Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 19.22 Sequence of New Bit Rate Selection (6) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order in response to the transition to the programming/erasing state command. On completion of this erasure, ACK will be returned and a transition made to the programming/erasing state. Before sending the programming selection command or program data, the host should select the LSI device with the device selection command, the clock mode with the clock mode selection command, and the new bit rate with the new bit rate selection command, and then send the transition to programming/erasing state command. Rev. 1.00 Sep. 21, 2006 Page 533 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Command H'40 * Command, H'40 (1 byte): Transition to programming/erasing state Response H'06 * Response, H'06 (1 byte): Response to transition to programming/erasing state. The boot program will return ACK when the user MAT and user boot MAT have been erased normally by the transferred erasing program. Error Response H'C0 H'51 * Error response, H'C0 (1 byte): Error response to blank check of user boot MAT * Error code, H'51 (1 byte): Erasing error An error occurred and erasure was not completed. (7) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock mode selection command before a device selection command, or an inquiry command after the transition to programming/erasing state command, are such examples. Error Response H'80 H'xx * Error response, H'80 (1 byte): Command error * Command, H'xx (1 byte): Received command (8) Command Order The order for commands in the inquiry/selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device selection (H'10) command. 3. A clock mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the division ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit rate selection. 6. A new bit rate should be selected with the new bit rate selection (H'3F) command, according to the returned information on division ratios and operating frequencies. Rev. 1.00 Sep. 21, 2006 Page 534 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 7. After selection of the device and clock mode, programming/erasing information of the user boot MAT and user MAT should be inquired using the user boot MAT information inquiry (H'24), user MAT information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. (9) Programming/Erasing State In the programming/erasing state, a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed in table 19.12. Table 19.12 Programming/Erasing Commands Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name Description User boot MAT programming selection Transfers the user boot MAT programming program User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the sum of the user boot MAT Checks the sum of the user MAT Checks whether the contents of the user boot MAT are blank Checks whether the contents of the user MAT are blank Inquires into the boot program's processing status Rev. 1.00 Sep. 21, 2006 Page 535 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Programming: Programming is executed by a programming-selection command and a 128-byte programming command. First, the host should send the programming-selection command, and select the programming method and programming MATs. There are two programming selection commands according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the program data according to the method specified by the selection command. When more than 128 bytes of data are to be programmed, 128-byte programming commands should be executed repeatedly. Sending from the host a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. In case of continuing programming with another method or programming of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 19.23. Host Programming selection (H'42, H'43) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Programming ACK 128-byte programming (H'FFFFFFFF) ACK Repeat Figure 19.23 Programming Sequence Rev. 1.00 Sep. 21, 2006 Page 536 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (a) User Boot MAT Programming Selection The boot program will transfer a programming program in response to the user boot MAT programming selection command. The data is programmed to the user boot MAT by the transferred programming program. Command H'42 * Command, H'42 (1 byte): User boot MAT programming selection Response H'06 * Response, H'06 (1 byte): Response to user boot MAT programming selection. When the programming program has been transferred, the boot program will return ACK. Error Response H'C2 ERROR * Error response, H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) User MAT Programming Selection: The boot program will transfer a programming program in response to the user MAT programming selection command. The data is programmed to the user MAT by the transferred programming program. Command H'43 * Command, H'43 (1 byte): User MAT programming selection Response H'06 * Response, H'06 (1 byte): Response to user MAT programming selection. When the programming program has been transferred, the boot program will return ACK. Error Response H'C3 ERROR * Error response, H'C3 (1 byte): Error response to user MAT programming selection * ERROR (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) 128-Byte Programming The boot program will use the programming program transferred by the programming selection command for programming the user boot MAT or user MAT in response to the 128-byte programming command. Rev. 1.00 Sep. 21, 2006 Page 537 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Command H'50 Data *** SUM Address *** * Command, H'50 (1 byte): 128-byte programming * Programming address (4 bytes): Start address for programming. Multiple of the size specified in response to the programming unit inquiry command. (e.g. H'00, H'01, H'00, H'00: H'010000) * Program data (128 bytes): Data to be programmed. The size is specified in response to the programming unit inquiry command. * SUM (1 byte): Checksum Response H'06 * Response, H'06 (1 byte): Response to 128-byte programming. On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error response, H'D0 (1 byte): Error response to 128-byte programming * ERROR (1 byte): Error code H'11: Checksum Error H'2A: Address error H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the boundary of the programming unit. For example, when the programming unit is 128 bytes, the lower eight bits of the address should be H'00 or H'80. When the program data is less than 128 bytes, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of programming and wait for selection of programming or erasing. Command H'50 Address SUM * Command, H'50 (1 byte): 128-byte programming * Programming address (4 bytes): End code (H'FF, H'FF, H'FF, H'FF) * SUM (1 byte): Checksum Rev. 1.00 Sep. 21, 2006 Page 538 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Response H'06 * Response, H'06 (one byte): Response to 128-byte programming. On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error response, H'D0 (1 byte): Error response to 128-byte programming * ERROR (1 byte): Error code H'11: Checksum error H'2A: Address error H'53: Programming error An error has occurred in programming and programming cannot be continued. (10) Erasure Erasure is performed with the erasure selection and block erasure commands. First, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure processing. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection command and block erasure command is shown in figure 19.24. Rev. 1.00 Sep. 21, 2006 Page 539 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Host Preparation for erasure (H'48) Boot program Transfer of erasure program ACK Erasure (Erase-block number) ACK Erasure (H'FF) ACK Repeat Erasure Figure 19.24 Erasure Sequence (a) Erasure Selection The boot program will transfer the erasing program in response to the erasure selection command. User MAT data is erased by the transferred erasing program. Command H'48 * Command, H'48 (1 byte): Erasure selection Response H'06 * Response, H'06 (1 byte): Response to erasure selection. After the erasing program has been transferred, the boot program will return ACK. Error Response H'C8 ERROR * Error response, H'C8 (1 byte): Error response to erasure selection * ERROR (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) Block Erasure The boot program will erase the contents of the specified block in response to the block erasure command. Rev. 1.00 Sep. 21, 2006 Page 540 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Command H'58 Size Block number SUM * Command, H'58 (1 byte): Erasure * Size (1 byte): The number of characters that represents the erase-block number. Fixed at 1. * Block number (1 byte): Number of the block to be erased * SUM (1 byte): Checksum Response H'06 * Response, H'06 (1 byte): Response to erasure On completion of erasure, the boot program will return ACK. Error Response H'D8 ERROR * Error response, H'D8 (1 byte): Response to erasure * ERROR (1 byte): Error code H'11: Checksum error H'29: Block number error Block number is incorrect. H'51: Erasing error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM * Command, H'58 (1 byte): Erasure * Size (1 byte): The number of characters that represents the block number. Fixed at 1. * Block number (1 byte): H'FF Stop code for erasure * SUM (1 byte): Checksum Response H'06 * Response, H'06 (1 byte): Response to end of erasure (ACK will be returned) When erasure is to be performed again after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Rev. 1.00 Sep. 21, 2006 Page 541 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) (11) Memory Read The boot program will return the data in the specified address in response to the memory read command. Command H'52 Size Area Read address SUM Read size * Command, H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (one byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum Response H'52 Data SUM Read size *** * * * * Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data of the read size from the read address SUM (1 byte): Checksum H'D2 ERROR Error Response * Error response: H'D2 (1 byte): Error response to memory read * ERROR (1 byte): Error code H'11: Checksum error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (12) User Boot MAT Sum Check The boot program will return the total amount of bytes of the user boot MAT contents in response to the user boot MAT sum check command. Rev. 1.00 Sep. 21, 2006 Page 542 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Command H'4A * Command, H'4A (1 byte): Sum check for user boot MAT Response H'5A Size Checksum of MAT SUM * Response, H'5A (1 byte): Response to the checksum of user boot MAT * Size (1 byte): The number of characters that represents the checksum. Fixed at 4. * Checksum of MAT (4 bytes): Checksum of user boot MATs. The total amount of data is obtained in byte units. * SUM (1 byte): Checksum (for transmit data) (13) User MAT Sum Check The boot program will return the total amount of bytes of the user MAT contents in response to the user MAT sum check command. Command H'4B * Command, H'4B (1 byte): Checksum for user MAT Response H'5B Size Checksum of MAT SUM * Response, H'5B (1 byte): Response to the checksum of the user MAT * Size (1 byte): The number of characters that represents the checksum. Fixed at 4. * Checksum of MAT (4 bytes): Checksum of user MATs. The total amount of data is obtained in byte units. * SUM (1 byte): Checksum (for transmit data) (14) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result in response to the user boot MAT blank check command. Command H'4C * Command, H'4C (1 byte): Blank check for user boot MATs Response H'06 * Response, H'06 (1 byte): Response to blank check of user boot MATs. If all user boot MATs are blank (H'FF), the boot program will return ACK. Rev. 1.00 Sep. 21, 2006 Page 543 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Error Response H'CC H'52 * Error response, H'CC (1 byte): Error response to blank check for user boot MATs * Error code, H'52 (1 byte): Erasure incomplete error (15) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result in response to the user MAT blank check command. Command H'4D * Command, H'4D (1 byte): Blank check for user MATs Response H'06 * Response, H'06 (1 byte): Response to blank check for user MATs. If all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CD H'52 * Error response, H'CD (1 byte): Error response to blank check for user MATs * Error code, H'52 (1 byte): Erasure incomplete error (16) Boot Program State Inquiry The boot program will return indications of its present state and error condition in response to the boot program state inquiry command. This inquiry can be made in either the inquiry/selection state or the programming/erasing state. Command H'4F * Command, H'4F (1 byte): Inquiry regarding boot program's state Response H'5F Size Status ERROR SUM * * * * Response, H'5F (1 byte): Response to boot program state inquiry Size (1 byte): The number of characters. Fixed at 2. Status (1 byte): State of the standard boot program ERROR (1 byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (1 byte): Checksum Rev. 1.00 Sep. 21, 2006 Page 544 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Table 19.13 Status Code Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device Selection Wait Clock Mode Selection Wait Bit Rate Selection Wait Programming/Erasing State Transition Wait (Bit rate selection is completed) Programming/Erasing State Programming/Erasing Selection Wait (Erasure is completed) Program Data Receive Wait (Programming is completed) Erase Block Specification Wait (Erasure is completed) Table 19.14 Error Code Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No Error Checksum Error Program Size Error Device Code Mismatch Error Clock Mode Mismatch Error Bit Rate Selection Error Input Frequency Error Division Ratio Error Operating Frequency Error Block Number Error Address Error Data Length Error Erasing Error Erasure Incomplete Error Programming Error Selection Processing Error Command Error Bit-Rate-Adjustment Confirmation Error Rev. 1.00 Sep. 21, 2006 Page 545 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 19.9 Usage Notes 1. The initial state of a Renesas product at shipment is the erased state. For a product whose history of erasing is undefined, automatic erasure for checking the initial state (erased state) and compensating is recommended. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index of the PROM programmer does not match the specifications, excessive current flows and the product may be damaged. 4. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports a programming voltage of 3.3 V for Renesas microcomputers with 512-Kbyte flash memory. Do not set the programmer to HN28F101 or a programming voltage of 5.0 V. Use only the specified socket adapter. If other adapters are used, the product may be damaged. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing. As a high voltage is applied to the flash memory during programming/erasing, doing so may damage flash memory permanently. If a reset is input accidentally, the reset must be released after a reset period of 100 s which is longer than normal. 6. After programming/erasing, access to the flash memory is prohibited until FKEY is cleared. In case the LSI mode is changed to generate a reset on completion of a programming/erasing operation, a reset state (RES = 0) of 100 s or more must be secured. Transitions to the reset state or hardware standby mode are prohibited during programming/erasing operations. However, when the reset signal is accidentally input to the chip, the reset must be released after a reset period of 100 s that is longer than normal. 7. At turning on or off the VCC power supply, fix the RES pin to low and set the flash memory to the hardware protection state. This power-on or power-off timing must also be satisfied at a power-off or power-on caused by a power failure and other factors. 8. Perform programming to a 128-byte programming-unit block only once in on-board programming or programmer mode. Perform programming in the state where the programming-unit block is fully erased. 9. When a chip is to be reprogrammed with the programmer after it has already been programmed or erased in on-board programming mode, automatic programming is recommended to be performed after automatic erasure. 10. To write data or programs to the flash memory, program data and programs must be allocated to addresses higher than that of the external interrupt vector table (in normal mode: H'0020, in advanced mode: H'000040), and H'FF must be written to the areas that are reserved for the system in the exception handling vector table. Rev. 1.00 Sep. 21, 2006 Page 546 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) 11. If data other than H'FF (4 bytes) is written to the key code area (in normal mode: H'001E to H'001F, in advance mode: H'00003C to H'00003F) of flash memory, reading cannot be performed in programmer mode. (In this case, data is read as H'00. Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to write H'FF to the entire key code area. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and version of program. 12. The code size of the programming program that includes the initialization routine or the erasing program that includes the initialization routine is 2 Kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 200 s at the maximum. 13. While an instruction in the on-chip RAM is being executed, the DTC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage the on-chip RAM or a MAT switchover may occur and the CPU get out of control. Do not use the DTC to write to flash memory related registers. 14. A programming/erasing program for flash memory used in the conventional H8S F-ZTAT microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this H8S F-ZTAT microcomputer. 15. Unlike the conventional H8S F-ZTAT microcomputer, no countermeasures are available for a runaway by the WDT during programming/erasing. Prepare countermeasures (e.g. use of periodic timer interrupts) for the WDT with taking the programming/erasing time into consideration as required. Rev. 1.00 Sep. 21, 2006 Page 547 of 658 REJ09B0310-0100 Section 19 Flash Memory (0.18-m F-ZTAT Version) Rev. 1.00 Sep. 21, 2006 Page 548 of 658 REJ09B0310-0100 Section 20 PROM (OTP Version) Section 20 PROM (OTP Version) The R4P2125 has 512-Kbyte one-time programmable on-chip flash memory. The PROM is connected to the bus master and a 16-bit width data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. The mode pins (MD2*, MD1, and MD0) and the EXPE bit in MDCR can be set to enable or disable the on-chip PROM. For details on MDCR, see section 3.2.1, Mode Control Register (MDCR). The R4P/2125 is programmable using the PROM programmer. Note: * MD2 is not supported in SDIP-64 and QFP-64. Figure 20.1 shows a block diagram of the PROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'07FFFE H'07FFFF Figure 20.1 PROM Block Diagram (R4P2125) Rev. 1.00 Sep. 21, 2006 Page 549 of 658 REJ09B0310-0100 Section 20 PROM (OTP Version) 20.1 20.1.1 Programmer Mode Programmer Mode Setting Programs and data can be written in programmer mode. In programmer mode, the on-chip PROM can be freely programmed using a PROM programmer that supports Renesas microcomputer device types with 512-Kbyte on-chip flash memory. 20.1.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the PROM programmer to match the packages concerned. For the socket adapter, confirm with a programmer manufacturer supporting the Renesas microcomputer device type with 512-Kbyte on-chip flash memory. Figure 20.2 shows the memory map in programmer mode. For pin names in programmer mode, see table 1.1. MCU mode H'000000 Programmer mode H'00000 R4P2125 On-chip PROM area H'07FFFF H'7FFFF Figure 20.2 Memory Map in Programmer Mode Rev. 1.00 Sep. 21, 2006 Page 550 of 658 REJ09B0310-0100 Section 20 PROM (OTP Version) 20.2 Usage Notes 1. The initial state of a Renesas product at shipment is the erased state. For a product whose history of erasing is undefined, automatic erasure for checking the initial state (erased state) and compensating is recommended. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index of the PROM programmer does not match the specifications, excessive current flows and the product may be damaged. 4. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports a programming voltage of 3.3 V for Renesas microcomputers with 512-Kbyte flash memory. Do not set the programmer to HN28F101 or a programming voltage of 5.0 V. Use only the specified socket adapter. If other adapters are used, the product may be damaged. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing. As a high voltage is applied to the flash memory during programming/erasing, doing so may damage flash memory permanently. If a reset is input accidentally, the reset must be released after a reset period of 100 s which is longer than normal. Rev. 1.00 Sep. 21, 2006 Page 551 of 658 REJ09B0310-0100 Section 20 PROM (OTP Version) Rev. 1.00 Sep. 21, 2006 Page 552 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator Section 21 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (), internal clock, bus master clock, and subclock (SUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and subclock waveform forming circuit. Figure 21.1 shows a block diagram of the clock pulse generator. EXTAL XTAL Oscillator Duty correction circuit System clock select circuit Mediumspeed clock divider /2 to /32 Bus master clock select circuit EXCL Subclock input circuit Subclock waveform forming circuit SUB WDT_1 count clock System clock to pin Internal clock to on-chip peripheral modules Bus master clock to CPU and DTC Figure 21.1 Block Diagram of Clock Pulse Generator In high-speed mode or medium-speed mode, the bus master clock is selected by software according to the settings of the SCK2 to SCK0 bits in the standby control register (SBYCR). For details on SBYCR, see section 22.1.1, Standby Control Register (SBYCR). The subclock input is controlled by software according to the setting of the EXCLE bit in the low power control register (LPWRCR). For details on LPWRCR, see section 22.1.2, Low-Power Control Register (LPWRCR). CPG0500A_000020020300 Rev. 1.00 Sep. 21, 2006 Page 553 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator 21.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 21.1.1 Connecting Crystal Resonator Figure 21.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance Rd, given in table 21.1 should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 21.3 shows an equivalent circuit of a crystal resonator. A crystal resonator having the characteristics given in table 21.2 should be used. The frequency of the crystal resonator should be the same as that of the system clock (). CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 21.2 Typical Connection to Crystal Resonator Table 21.1 Damping Resistor Values Frequency (MHz) Rd () 8 200 10 0 12 0 16 0 20 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator C0 Figure 21.3 Equivalent Circuit of Crystal Resonator Rev. 1.00 Sep. 21, 2006 Page 554 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator Table 21.2 Crystal Resonator Parameters Frequency (MHz) RS (max.) () C0 (max.) (pF) 8 80 10 70 12 60 7 16 50 20 40 21.1.2 External Clock Input Method Figure 21.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 21.3. The frequency of the external clock should be the same as that of the system clock (). EXTAL XTAL External clock input Open (a) Example of external clock input when XTAL pin is left open EXTAL XTAL External clock input (b) Example of external clock input when an inverted clock is input to XTAL pin Figure 21.4 Example of External Clock Input Rev. 1.00 Sep. 21, 2006 Page 555 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator Table 21.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Clock pulse width low level Clock pulse width high level Symbol tEXL tEXH tEXr tEXf tCL tCH Min. 20 20 0.4 0.4 Max. 5 5 0.6 0.6 Unit ns ns ns ns tcyc tcyc Figure 24.4 Test Conditions Figure 21.5 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 21.5 External Clock Input Timing The oscillator and duty correction circuit can adjust the waveform of the external clock input that is input from the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to maintain the reset state. Table 21.4 shows the external clock output stabilization delay time. Figure 21.6 shows the timing of the external clock output stabilization delay time. Rev. 1.00 Sep. 21, 2006 Page 556 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator Table 21.4 External Clock Output Stabilization Delay Time Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Item Symbol Min. 500 Max. Unit s Remarks Figure 21.6 External clock output stabilization delay tDEXT* time Note: * tDEXT includes a RES pulse width (tRESW). VCC 3.0 V STBY VIH EXTAL (Internal and external) RES tDEXT* Note: The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 21.6 Timing of External Clock Output Stabilization Delay Time Rev. 1.00 Sep. 21, 2006 Page 557 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator 21.2 Duty Correction Circuit The duty correction circuit generates the system clock () by correcting the duty of the clock output from the oscillator. 21.3 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock (), and generates /2, /4, /8, /16, and /32 clocks. 21.4 Bus Master Clock Select Circuit The bus master clock select circuit selects a clock to supply to the bus master from either the system clock () or medium-speed clock (/2, /4, /8, /16, or /32) by the SCK2 to SCK0 bits in SBYCR. Rev. 1.00 Sep. 21, 2006 Page 558 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator 21.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. Figure 21.7 shows the relationship of subclock input from the EXCL pin. When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the pin to 0. The subclock input is enabled by setting the EXCLE bit in LPWRCR to 1. EXCLE (LPWRCR) P46/EXCL Subclock Figure 21.7 Subclock Input from EXCL Pin Subclock input conditions are shown in table 21.5. When the subclock is not used, subclock input should not be enabled. Table 21.5 Subclock Input Conditions VCC = 3.0 to 3.6 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min. Typ. 15.26 15.26 Max. 10 10 Unit s s ns ns Test Conditions Figure 21.8 tEXCLH tEXCLL EXCL VCC x 0.5 tEXCLr tEXCLf Figure 21.8 Subclock Input Timing Rev. 1.00 Sep. 21, 2006 Page 559 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator 21.6 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL pin, the subclock waveform forming circuit samples the subclock using a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in subactive mode, subsleep mode, or watch mode. 21.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by the oscillator to which the XTAL and EXTAL pins are connected is selected as a system clock () when returning from high-speed mode, medium-speed mode, sleep mode, the reset state, or standby mode. In subactive mode, subsleep mode, or watch mode, a subclock input from the EXCL pin is selected as a system clock when the EXCLE bit in LPWRCR is 1. At this time, on-chip peripheral modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, I/O ports, and interrupt controller and their functions operate on the SUB clock. The count clock and sampling clock for each timer are divided SUB clocks. Rev. 1.00 Sep. 21, 2006 Page 560 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator 21.8 21.8.1 Usage Notes Notes on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings that vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not exceed the maximum rating. 21.8.2 Notes on Board Design When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator to prevent inductive interference with correct oscillation as shown in figure 21.9. Signal A CL2 XTAL EXTAL CL1 Signal B This LSI Prohibited Figure 21.9 Note on Board Design of Oscillator Section Rev. 1.00 Sep. 21, 2006 Page 561 of 658 REJ09B0310-0100 Section 21 Clock Pulse Generator Rev. 1.00 Sep. 21, 2006 Page 562 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Section 22 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16, or /32. * Subactive mode The CPU operates based on the subclock, and on-chip peripheral modules TMR_0, TMR_1, WDT_0, and WDT_1 continue operating. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Subsleep mode The CPU stops but on-chip peripheral modules TMR_0, TMR_1, WDT_0, and WDT_1 continue operating. * Watch mode The CPU stops but on-chip peripheral module WDT_1 continue operating. * Software standby mode The clock pulse generator stops, and the CPU and on-chip peripheral modules stop operating. * Hardware standby mode The clock pulse generator stops, and the CPU and on-chip peripheral modules enter the reset state. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually. Rev. 1.00 Sep. 21, 2006 Page 563 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). For details on the PSS bit in TSCR_1 (WDT_1), see TCSR_1 in section 14.3.2, Timer Control/Status Register (TCSR). * * * * * * Standby control register (SBYCR) Low power control register (LPWRCR) Module stop control register H (MSTPCRH) Module stop control register L (MSTPCRL) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Standby Control Register (SBYCR) 22.1.1 SBYCR controls power-down modes. Bit 7 Initial Bit Name Value SSBY 0 R/W R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode, subactive mode, or watch mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode 1: Shifts to watch mode or high-speed mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt. Rev. 1.00 Sep. 21, 2006 Page 564 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Bit 6 5 4 Initial Bit Name Value STS2 STS1 STS0 0 0 0 R/W R/W R/W R/W Description Standby Timer Select 2 to 0 On canceling software standby mode, watch mode, or subactive mode, these bits select the wait time for clock stabilization from clock oscillation start. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 22.1 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, an arbitrary wait time can be selected. For normal cases, the minimum value is recommended. 3 2 1 0 SCK2 SCK1 SCK0 0 0 0 0 R/W R/W R/W R/W Reserved The initial value should not be changed. System Clock Select 2 to 0 These bits select a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, these bits must be cleared to B'000. 000: High-speed mode 001: Medium-speed clock: /2 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11X: Setting prohibited [Legend] X: Don't care Rev. 1.00 Sep. 21, 2006 Page 565 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Table 22.1 Operating Frequency and Wait Time STS2 0 0 0 0 1 1 1 1 Note: STS1 0 0 1 1 0 0 1 1 STS0 0 1 0 1 0 1 0 1 Wait Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 20 MHz 0.4 0.8 1.6 3.3 6.6 13.1 0.8 10 MHz 0.8 1.6 3.3 6.6 13.1 26.2 1.6 8 MHz 1.0 2.0 4.1 8.2 16.4 32.8 2.0 s Unit ms Recommended specification * Setting prohibited. 22.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit 7 Initial Bit Name Value DTON 0 R/W Description R/W Direct Transfer On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts directly to subactive mode, or shifts to sleep mode or software standby mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode or watch mode 1: Shifts directly to high-speed mode, or shifts to subsleep mode Rev. 1.00 Sep. 21, 2006 Page 566 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Bit 6 Initial Bit Name Value LSON 0 R/W R/W Description Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts to watch mode or subactive mode When the SLEEP instruction is executed in subactive mode: 0: Shifts directly to watch mode or high-speed mode 1: Shifts to subsleep mode or watch mode When watch mode is cancelled: 0: Shifts to high-speed mode 1: Shifts to subactive mode 5 NESEL 0 R/W Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL pin is sampled using the clock () generated by the system clock pulse generator. 0: Sampling using /32 clock 1: Sampling using /4 clock 4 EXCLE 0 R/W Subclock Input Enable Enables or disables subclock input from the EXCL pin. 0: Disables subclock input from the EXCL pin 1: Enables subclock input from the EXCL pin 3 to 0 All 0 R/W Reserved The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 567 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, and MSTPCRB) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Data transfer controller (DTC) 16-bit free-running timer (FRT) 8-bit timers (TMR_0 and TMR_1) 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) Reserved The initial value should not be changed. A/D converter 8-bit timers (TMR_X and TMR_Y) * MSTPCRL Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Serial communication interface 0 (SCI_0) Serial communication interface 1 (SCI_1) Reserved The initial value should not be changed. I2C bus interface channel 0 (IIC_0) I2C bus interface channel 1 (IIC_1) Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Rev. 1.00 Sep. 21, 2006 Page 568 of 658 REJ09B0310-0100 Section 22 Power-Down Modes * MSTPCRA Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTPA7 0 MSTPA6 0 MSTPA5 0 MSTPA4 0 MSTPA3 0 MSTPA2 0 MSTPA1 0 MSTPA0 0 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. 14-bit PWM timer (PWMX) 8-bit PWM timer (PWM) MSTPCRH and MSTPCRA set operation or stop by a combination of bits as follows: MSTPCRH: MSTP11 0 0 1 1 MSTPCRA: MSTPA1 0 1 0 1 Function 14-bit PWM timer (PWMX) operates. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. MSTPCRH: MSTP11 0 0 1 1 MSTPCRA: MSTPA0 0 1 0 1 Function 8-bit PWM timer (PWM) operates. 8-bit PWM timer (PWM) stops. 8-bit PWM timer (PWM) stops. 8-bit PWM timer (PWM) stops. Note: The MSTP11 bit in MSTPCRH is the module stop bit of PWM and PWMX. Rev. 1.00 Sep. 21, 2006 Page 569 of 658 REJ09B0310-0100 Section 22 Power-Down Modes * MSTPCRB Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTPB7 1 MSTPB6 1 MSTPB5 1 MSTPB4 1 MSTPB3 1 MSTPB2 1 MSTPB1 1 MSTPB0 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. 16-bit cycle measurement timer 1 (TCM_1) 16-bit cycle measurement timer 0 (TCM_0) 22.2 Mode Transitions and LSI States Figure 22.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 22.2 shows the LSI internal states in each operating mode. Rev. 1.00 Sep. 21, 2006 Page 570 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Program halt state STBY pin = Low Reset state Hardware standby mode STBY pin = High RES pin = Low Program execution state RES pin = High SLEEP instruction SSBY = 0, LSON = 0 Sleep mode (main clock) High-speed mode (main clock) SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 Any interrupt SLEEP instruction External interrupt*3 SLEEP instruction Interrupt*1 LSON bit = 0 SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SLEEP instruction Interrupt*1 LSON bit = 1 SLEEP instruction Interrupt*2 SSBY = 0, PSS = 1, LSON = 1 Subsleep mode (subclock) SSBY = 1, PSS = 0, LSON = 0 Software standby mode Medium-speed mode (main clock) SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception processing SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception processing Subactive mode (subclock) : Transition after exception processing : Power-down mode Notes: * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * Always select high-speed mode before making a transition to watch mode or subactive mode. 1. NMI, IRQ0 to IRQ7, and WDT_1 interrupts 2. NMI, IRQ0 to IRQ7, WDT_0, WDT_1, TMR_0, and TMR_1 interrupts 3. NMI and IRQ0 to IRQ7 interrupts Figure 22.1 Mode Transition Diagram Rev. 1.00 Sep. 21, 2006 Page 571 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Table 22.2 LSI Internal States in Each Operating Mode Function System clock pulse generator Subclock input HighSpeed Functioning Functioning Functioning MediumSpeed Sleep Functioning Functioning Functioning in mediumspeed mode Functioning Functioning Functioning Halted Module Stop Functioning Functioning Functioning Watch Halted Subactive Halted Subsleep Halted Software Standby Halted Hardware Standby Halted Functioning Halted Functioning Subclock operation Functioning Halted Halted Halted CPU Instruction execution Registers Halted Halted Retained Retained Retained Retained Undefined External NMI interrupts IRQ0 to IRQ7 On-chip DTC peripheral modules Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Functioning Functioning in mediumspeed mode/ Functioning Functioning Functioning Function- Halted ing/Halted (retained) (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) WDT_1 Functioning Functioning Functioning Subclock operation Halted (retained) Subclock operation Subclock operation Halted (retained) Halted (reset) WDT_0 TMR_0, TMR_1 FRT TCM TMR_X, TMR_Y IIC_0 IIC_1 Functioning/Halted (retained) Halted (retained) Halted (retained) Rev. 1.00 Sep. 21, 2006 Page 572 of 658 REJ09B0310-0100 Section 22 Power-Down Modes HighSpeed Functioning Function On-chip PWM peripheral PWMX modules SCI_0 SCI_1 A/D converter RAM MediumSpeed Sleep Functioning Functioning Module Stop Watch Subactive Halted (reset) Subsleep Halted (reset) Software Hardware Standby Standby Halted (reset) Halted (reset) Function- Halted ing/Halted (reset) (reset) Functioning Functioning Functioning Functioning Functioning (DTC) Functioning Functioning Functioning Retained Functioning Functioning Retained Retained Retained I/O Retained Functioning Retained High impedance Note: Halted (retained) means that the internal register values are retained and the internal state is operation suspended. Halted (reset) means that the internal register values and the internal state are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Rev. 1.00 Sep. 21, 2006 Page 573 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the operating clock can be selected from /2, /4, /8, /16, or /32. On-chip peripheral modules other than the bus masters operate on the system clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in four states, and internal I/O registers in eight states. By clearing all of bits SCK2 to SCK0 to 0 in medium-speed mode, a transition is made to highspeed mode at the end of the current bus cycle. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0 and the LSON bit in LPWRCR cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, medium-speed mode is cancelled and a transition is made to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 21, 2006 Page 574 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Figure 22.2 shows an example of medium-speed mode timing. Medium-speed mode , peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 22.2 Medium-Speed Mode Timing 22.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the on-chip peripheral modules do not. The contents of the CPU's internal registers are retained. Sleep mode is cleared by any interrupt, the RES pin input, or the STBY pin input. When an interrupt occurs, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the interrupt is disabled, or interrupts other than NMI have been masked by the CPU. When the RES pin is driven low and sleep mode is cleared, a transition is made to the reset state. After the specified reset input time has elapsed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 21, 2006 Page 575 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU registers, on-chip RAM data, I/O ports, and the states of on-chip peripheral modules other than the SCI, PWM, PWMX, and A/D converter are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7), RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding enable bit to 1. In the case of an IRQ0 to IRQ7 interrupt, software standby mode is not cleared if the corresponding enable bit is cleared to 0 or if the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, software standby mode is cleared and a transition is made to hardware standby mode. Rev. 1.00 Sep. 21, 2006 Page 576 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Figure 22.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin. Oscillator NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 22.3 Software Standby Mode Application Example Rev. 1.00 Sep. 21, 2006 Page 577 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2*, MD1, and MD0) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, the clock pulse generator starts oscillation. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is subsequently driven high after the clock oscillation stabilization time has elapsed, reset exception handling starts. Figure 22.4 shows an example of hardware standby mode timing. Note: * MD2 is not supported in SDIP-64 and QFP-64. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 22.4 Hardware Standby Mode Timing Rev. 1.00 Sep. 21, 2006 Page 578 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and on-chip peripheral modules other than WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is cleared by an interrupt (WOVI1, NMI, IRQ0 to IRQ7), RES pin input, or STBY pin input. When an interrupt occurs, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR cleared to 0, or a transition is made to subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ7 interrupt, watch mode is not cleared if the corresponding enable bit has been cleared to 0 or the interrupt has been masked by the CPU. In the case of an interrupt from an on-chip peripheral module, watch mode is not cleared if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 21, 2006 Page 579 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. On-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. The contents of the CPU registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Subsleep mode is cleared by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to IRQ7), RES pin input, or STBY pin input. When an interrupt occurs, subsleep mode is cleared and interrupt exception handling starts. In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not cleared if the corresponding enable bit has been cleared to 0 or the interrupt has been masked by the CPU. In the case of an interrupt from an on-chip peripheral module, subsleep mode is not cleared if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 21, 2006 Page 580 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR both set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode with the LSON bit in LPWRCR set to 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at a low speed based on the subclock and sequentially executes programs. On-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must all be cleared to 0. Subactive mode is cleared by the SLEEP instruction, RES pin input, or STBY pin input. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, subactive mode is cleared and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode. For details on direct transitions, see section 22.11, Direct Transitions. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Sep. 21, 2006 Page 581 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle. In module stop mode, the internal states of on-chip peripheral modules other than the SCI, PWM, PWMX, and A/D converter are retained. After the reset state is cancelled, all on-chip peripheral modules other than the DTC are in module stop mode. While an on-chip peripheral module is in module stop mode, its registers cannot be read from or written to. 22.11 Direct Transitions The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a direct transition is made from high-speed mode to subactive mode and vice versa, there is no interruption of program execution. A direct transition is enabled by executing the SLEEP instruction after setting the DTON bit in LPWRCR to 1. After a transition, direct transition exception handling starts. When the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR both set to 1, and the PSS bit in TSCR (WDT_1) set to 1, the CPU makes a direct transition to subactive mode. When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, the DTON bit in LPWRCR set to 1, and the PSS bit in TSCR (WDT_1) set to 1, after the time set in the STS2 to STS0 bits in SBYCR has elapsed, the CPU makes a direct transition to high-speed mode. Rev. 1.00 Sep. 21, 2006 Page 582 of 658 REJ09B0310-0100 Section 22 Power-Down Modes 22.12 Usage Notes 22.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, while a high level is output or the pull-up MOS is on, the current consumption is not reduced by the amount of current to support the high level output. 22.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. 22.12.3 DTC Module Stop Mode If the DTC module stop mode specification and DTC bus request occur simultaneously, the bus is released to the DTC and the MSTP bit cannot be set to 1. After completing the DTC bus cycle, set the MSTP bit to 1 again. Rev. 1.00 Sep. 21, 2006 Page 583 of 658 REJ09B0310-0100 Section 22 Power-Down Modes Rev. 1.00 Sep. 21, 2006 Page 584 of 658 REJ09B0310-0100 Section 23 List of Registers Section 23 List of Registers The list of registers gives information on the on-chip register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. For the addresses of 16 bits, the MSB is described. Registers are classified by functional modules. The access size is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * Each line covers eight bits, and 16-bit register is shown as 2 lines, respectively. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip module, see the section on that on-chip module. 4. Register selection conditions * Register selection conditions are described in the same order as the register addresses. * Register selection conditions are described in section 3.2.2, System Control Register (SYSCR), section 3.2.3, Serial Timer Control Register (STCR), section 21.1.3, Module Stop Control Register H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, and MSTPCRB), or register descriptions for each module. 5. Register addresses (classification by type of module) * The register addresses are described by modules. * The register addresses are described in channel order when the module has multiple channels. Rev. 1.00 Sep. 21, 2006 Page 585 of 658 REJ09B0310-0100 Section 23 List of Registers 23.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Number Register Name TCM timer counter_0 TCM cycle limit register_0 TCM input capture register_0 TCM input capture buffer register_0 TCM status register_0 TCM control register_0 TCM interrupt enable register_0 TCM timer counter_1 TCM cycle limit register_1 TCM input capture register_1 TCM input capture buffer register_1 TCM status register_1 TCM control register_1 TCM interrupt enable register_1 Port 6 noise canceller enable register Port 6 noise canceller mode control register Port 6 noise cancel cycle setting register Port 4 noise canceller enable register Port 4 noise canceller mode control register Port 4 noise cancel cycle setting register Module stop control register A Module stop control register B Abbreviation of Bits TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 P6NCE P6NCMC P6NCCS P4NCE P4NCMC P4NCCS MSTPCRA MSTPCRB 16 16 16 16 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 Address Module H'FBC0 H'FBC2 H'FBC4 H'FBC6 H'FBC8 H'FBC9 H'FBCA H'FBD0 H'FBD2 H'FBD4 H'FBD6 H'FBD8 H'FBD9 H'FBDA H'FE00 H'FE01 H'FE02 H'FE09 H'FE0A H'FE0B H'FE7E H'FE7F TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 PORT PORT PORT PORT PORT PORT SYSTEM SYSTEM Data Width 16 16 16 16 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 586 of 658 REJ09B0310-0100 Section 23 List of Registers Number Register Name Interrupt control register D Flash code control status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register Timer XY control register I C bus extended control register_0 I C bus extended control register_1 DDC switch register Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC vector register Address break control register Break address register A Break address register B Break address register C Peripheral clock select register 2 2 Abbreviation of Bits ICRD FCCS FPCS FECS FKEY FMATS FTDAR TCRXY ICXR_0 ICXR_1 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC PCSR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address Module H'FE87 H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE H'FEC6 H'FED4 H'FED5 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF82 INT ROM ROM ROM ROM ROM ROM TMR_XY IIC_0 IIC_1 IIC_0, IIC_1 INT INT INT INT INT INT DTC DTC DTC DTC DTC DTC INT INT INT INT PWM, PWMX Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 587 of 658 REJ09B0310-0100 Section 23 List of Registers Number Register Name Standby control register Low power control register Module stop control register H Module stop control register L Serial mode register_1 I C bus control register_1 Bit rate register_1 I C bus status register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Serial interface mode register_1 I C bus data register_1 Second slave address register_1 I C bus mode register_1 Slave address register_1 Timer interrupt enable register Timer control/status register Free-running counter Output control register A Output control register B Timer control register 2 2 2 2 Abbreviation of Bits SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC OCRA OCRB TCR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 Address Module H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF88 H'FF89 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF8E H'FF8E H'FF8F H'FF8F H'FF90 H'FF91 H'FF92 H'FF94 H'FF94 H'FF96 H'FF97 H'FF98 H'FF98 H'FF9A H'FF9A H'FF9C H'FF9C H'FF9E SYSTEM SYSTEM SYSTEM SYSTEM SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 IIC_1 IIC_1 IIC_1 IIC_1 FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Timer output compare control register TOCR Input capture register A Output control register AR Input capture register B Output control register AF Input capture register C Output compare register DM Input capture register D ICRA OCRAR ICRB OCRAF ICRC OCRDM ICRD Rev. 1.00 Sep. 21, 2006 Page 588 of 658 REJ09B0310-0100 Section 23 List of Registers Number Register Name PWMX (D/A) control register PWMX (D/A) data register AH PWMX (D/A) data register AL PWMX (D/A) counter H PWMX (D/A) data register BH PWMX (D/A) counter L PWMX (D/A) data register BL Timer control/status register_0 Timer control/status register_0 Timer counter_0 Timer counter_0 Port 1 pull-up MOS control register Port 2 pull-up MOS control register Port 3 pull-up MOS control register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port 7 input data register Interrupt enable register Abbreviation of Bits DACR DADRAH DADRAL DACNTH DADRBH DACNTL DADRBL TCSR_0 TCSR_0 TCNT_0 TCNT_0 P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P7PIN IER 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address Module H'FFA0 H'FFA0 H'FFA1 H'FFA6 H'FFA6 H'FFA7 H'FFA7 H'FFA8 (write) H'FFA8 (read) H'FFA8 (write) H'FFA9 (read) H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBE H'FFC2 PWMX PWMX PWMX PWMX PWMX PWMX PWMX WDT_0 WDT_0 WDT_0 WDT_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT INT Data Width 8 8 8 8 8 8 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 589 of 658 REJ09B0310-0100 Section 23 List of Registers Number Register Name Serial timer control register System control register Mode control register Bus control register Wait state control register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 PWM output enable register B PWM output enable register A PWM data polarity register B PWM data polarity register A PWM register select PWM data register 15 to 0 Serial mode register_0 I C bus control register_0 Bit rate register_0 I C bus status register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Serial interface mode register_0 2 2 Abbreviation of Bits STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR15 to 0 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address Module H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD8 H'FFD9 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE SYSTEM SYSTEM SYSTEM BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 PWM PWM PWM PWM PWM PWM SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 Data Width 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 590 of 658 REJ09B0310-0100 Section 23 List of Registers Number Register Name I C bus data register_0 Second slave address register_0 I C bus mode register_0 Slave address register_0 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register_1 Timer control/status register_1 Timer counter_1 Timer counter_1 Timer control register_X Timer control register_Y 2 2 Abbreviation of Bits ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCSR_1 TCNT_1 TCNT_1 TCR_X TCR_Y 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address Module H'FFDE H'FFDE H'FFDF H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA (write) H'FFEA (read) H'FFEA (write) H'FFEB (read) H'FFF0 H'FFF0 IIC_0 IIC_0 IIC_0 IIC_0 Data Width 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter WDT_1 WDT_1 WDT_1 WDT_1 TMR_X TMR_Y 16 8 16 8 8 8 Rev. 1.00 Sep. 21, 2006 Page 591 of 658 REJ09B0310-0100 Section 23 List of Registers Number Register Name Timer control/status register_X Timer control/status register_Y Input capture register R Time constant register A_Y Input capture register F Time constant register B_Y Timer counter_X Timer counter_Y Time constant register C Time constant register A_X Time constant register B_X Timer connection register I Timer connection register S Abbreviation of Bits TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y TCNT_X TCNT_Y TCORC TCORA_X TCORB_X TCONRI TCONRS 8 8 8 8 8 8 8 8 8 8 8 8 8 Address Module H'FFF1 H'FFF1 H'FFF2 H'FFF2 H'FFF3 H'FFF3 H'FFF4 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FFFE TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_X TMR_X TMR_X TMR_X, TMR_Y Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 592 of 658 REJ09B0310-0100 Section 23 List of Registers 23.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Abbreviation TCMCNT_0 Bit 7 Bit 15 Bit 7 TCMMLCM_0 Bit 15 Bit 7 TCMICR_0 Bit 15 Bit 7 TCMICRF_0 Bit 15 Bit 7 TCMCSR_0 TCMCR_0 TCMIER_0 TCMCNT_1 OVF CST OVIE Bit 15 Bit 7 TCMMLCM_1 Bit 15 Bit 7 TCMICR_1 Bit 15 Bit 7 TCMICRF_1 Bit 15 Bit 7 TCMCSR_1 TCMCR_1 TCMIER_1 P6NCE P6NCMC P6NCCS OVF CST OVIE P67NCE Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 MAXOVF POCTL Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CMF CPSPE Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKSEG IEDG TCMIPE Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKSEG IEDG TCMIPE P64NCE Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 ICPF TCMMDS ICPIE Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 ICPF TCMMDS ICPIE P63NCE Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 CKS2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 CKS2 P62NCE Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 CKS1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 CKS1 P61NCE Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 CKS0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 CKS0 P60NCE PORT TCM_1 Module TCM_0 MAXOVIE CMIE Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 MAXOVF POCTL Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CMF CPSPE MAXOVIE CMIE P66NCE P65NCE P67NCMC P66NCMC P65NCMC P64NCMC P63NCMC P62NCMC P61NCMC P60NCMC P6NCCK2 P6NCCK1 P6NCCK0 Rev. 1.00 Sep. 21, 2006 Page 593 of 658 REJ09B0310-0100 Section 23 List of Registers Register Abbreviation P4NCE P4NCMC P4NCCS MSTPCRA MSTPCRB ICRD FCCS FPCS FECS FKEY FMATS FTDAR TCRXY ICXR_0 ICXR_1 DDCSWR Bit 7 P47NCE Bit 6 P46NCE Bit 5 P45NCE Bit 4 P44NCE Bit 3 P43NCE Bit 2 P42NCE Bit 1 P41NCE Bit 0 P40NCE Module PORT P47NCMC P46NCMC P45NCMC P44NCMC P43NCMC P42NCMC P41NCMC P40NCMC MSTPA7 MSTPB7 ICRD7 FWE K7 MS7 TDER STOPIM STOPIM MSTPA6 MSTPB6 ICRD6 K6 MS6 TDA6 HNDS HNDS MSTPA5 MSTPB5 ICRD5 K5 MS5 TDA5 CKSX ICDRF ICDRF MSTPA4 MSTPB4 ICRD4 FLER K4 MS4 TDA4 CKSY ICDRE ICDRE MSTPA3 MSTPB3 ICRD3 K3 MS3 TDA3 ALIE ALIE CLR3 P4NCCK2 P4NCCK1 P4NCCK0 MSTPA2 MSTPB2 ICRD2 K2 MS2 TDA2 ALSL ALSL CLR2 MSTPA1 MSTPB1 ICRD1 K1 MS1 TDA1 FNC1 FNC1 CLR1 MSTPA0 MSTPB0 ICRD0 SCO PPVS EPVB K0 MS0 TDA0 FNC0 FNC0 CLR0 TMR_XY IIC_0 IIC_1 IIC_0, IIC_1 INT ROM SYSTEM ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA ICRA7 ICRB7 ICRC7 IRQ7F IRQ7SCB IRQ3SCB DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 SWDTE CMF A23 ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTVEC6 A22 ICRA5 ICRB5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTVEC5 A21 ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTVEC4 A20 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTVEC3 A19 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTVEC2 A18 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTVEC1 A17 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTVEC0 BIE A16 INT DTC INT Rev. 1.00 Sep. 21, 2006 Page 594 of 658 REJ09B0310-0100 Section 23 List of Registers Register Abbreviation BARB BARC PCSR Bit 7 A15 A7 Bit 6 A14 A6 Bit 5 A13 A5 PWCKXB Bit 4 A12 A4 PWCKXA Bit 3 A11 A3 MSTP11 MSTP3 STOP ACKE Bit 3 AL MPIE Bit 3 PER Bit 3 SDIR ICDR3 SVAX2 CKS0 SVA2 OCIAE OCFA Bit 11 Bit 3 Bit 11 Bit 3 BUFEA OEA Bit 11 Bit 3 Bit 2 A10 A2 PWCKB Bit 1 A9 A1 PWCKA Bit 0 A8 PWCKXC PWM, PWMX SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC SSBY DTON MSTP15 MSTP7 C/A ICE Bit 7 ESTP TIE Bit 7 TDRE Bit 7 ICDR7 SVAX6 MLS SVA6 ICIAE ICFA Bit 15 Bit 7 OCRA/ OCRB TCR TOCR ICRA/ OCRAR Bit 15 Bit 7 IEDGA ICRDMS Bit 15 Bit 7 STS2 LSON MSTP14 MSTP6 CHR IEIC Bit 6 STOP RIE Bit 6 RDRF Bit 6 ICDR6 SVAX5 WAIT SVA5 ICIBE ICFB Bit 14 Bit 6 Bit 14 Bit 6 IEDGB OCRAMS Bit 14 Bit 6 STS1 NESEL MSTP13 MSTP5 PE MST Bit 5 IRTR TE Bit 5 ORER Bit 5 ICDR5 SVAX4 CKS2 SVA4 ICICE ICFC Bit 13 Bit 5 Bit 13 Bit 5 IEDGC ICRS Bit 13 Bit 5 STS0 EXCLE MSTP12 MSTP4 O/E TRS Bit 4 AASX RE Bit 4 FER Bit 4 ICDR4 SVAX3 CKS1 SVA3 ICIDE ICFD Bit 12 Bit 4 Bit 12 Bit 4 IEDGD OCRS Bit 12 Bit 4 SCK2 MSTP10 MSTP2 MP BBSY Bit 2 AAS TEIE Bit 2 TEND Bit 2 SINV ICDR2 SVAX1 BC2 SVA1 OCIBE OCFB Bit 10 Bit 2 Bit 10 Bit 2 BUFEB OEB Bit 10 Bit 2 SCK1 MSTP9 MSTP1 CKS1 IRIC Bit 1 ADZ CKE1 Bit 1 MPB Bit 1 ICDR1 SVAX0 BC1 SVA0 OVIE OVF Bit 9 Bit 1 Bit 9 Bit 1 CKS1 OLVLA Bit 9 Bit 1 SCK0 MSTP8 MSTP0 CKS0 SCP Bit 0 ACKB CKE0 Bit 0 MPBT Bit 0 SMIF ICDR0 FSX BC0 FS CCLRA Bit 8 Bit 0 Bit 8 Bit 0 CKS0 OLVLB Bit 8 Bit 0 FRT IIC_1 SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 SYSTEM Module INT Rev. 1.00 Sep. 21, 2006 Page 595 of 658 REJ09B0310-0100 Section 23 List of Registers Register Abbreviation ICRB/ OCRAF ICRC/ OCRDM ICRD Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DACR DADRAH DADRAL DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P7PIN DA13 DA5 DACNT7 DA13 DACNT8 DA5 OVF Bit 7 P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR P47DDR P37DR P47DR P67DDR P67DR P77PIN Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 PWME DA12 DA4 DACNT6 DA12 DACNT9 DA4 WT/IT Bit 6 P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR P46DDR P36DR P46DR P66DDR P66DR P76PIN Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 DA11 DA3 DACNT5 DA11 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 DA10 DA2 DACNT4 DA10 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 OEB DA9 DA1 DACNT3 DA9 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 OEA DA8 DA0 DACNT2 DA8 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 OS DA7 CFS DACNT1 DA7 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 CKS DA6 DACNT0 DA6 REGS REGS CKS0 Bit 0 P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR P70PIN PORT WDT_0 PWMX Module FRT DACNT10 DACNT11 DACNT12 DACNT13 DA3 TME Bit 5 P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR P45DDR P35DR P45DR P65DDR P65DR P75PIN DA2 Bit 4 P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR P44DDR P34DR P44DR P64DDR P64DR P74PIN DA1 RST/NMI Bit 3 P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR P43DDR P33DR P43DR P63DDR P63DR P73PIN DA0 CKS2 Bit 2 P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR P72PIN CFS CKS1 Bit 1 P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR P71PIN Rev. 1.00 Sep. 21, 2006 Page 596 of 658 REJ09B0310-0100 Section 23 List of Registers Register Abbreviation IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR15 to 0 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 Bit 7 IRQ7E EXPE CMIEB CMIEB CMFB CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 OE15 OE7 OS15 OS7 PWCKE Bit 7 C/A ICE Bit 7 ESTP TIE Bit 7 TDRE Bit 7 Bit 6 IRQ6E IICX1 IOSE ICIS0 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 OE14 OE6 OS14 OS6 PWCKS Bit 6 CHR IEIC Bit 6 STOP RIE Bit 6 RDRF Bit 6 Bit 5 IRQ5E IICX0 INTM1 BRSTRM ABW OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 OE13 OE5 OS13 OS5 Bit 5 PE MST Bit 5 IRTR TE Bit 5 ORER Bit 5 Bit 4 IRQ4E IICE INTM0 BRSTS1 AST CCLR1 CCLR1 ADTE Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 OE12 OE4 OS12 OS4 Bit 4 O/E TRS Bit 4 AASX RE Bit 4 FER Bit 4 Bit 3 IRQ3E FLSHE XRST BRSTS0 WMS1 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 OE11 OE3 OS11 OS3 RS3 Bit 3 STOP ACKE Bit 3 AL MPIE Bit 3 PER Bit 3 SDIR Bit 2 IRQ2E NMIEG MDS2 WMS0 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 OE10 OE2 OS10 OS2 RS2 Bit 2 MP BBSY Bit 2 AAS TEIE Bit 2 TEND Bit 2 SINV Bit 1 IRQ1E ICKS1 MDS1 IOS1 WC1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 OE9 OE1 OS9 OS1 RS1 Bit 1 CKS1 IRIC Bit 1 ADZ CKE1 Bit 1 MPB Bit 1 Bit 0 IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 OE8 OE0 OS8 OS0 RS0 Bit 0 CKS0 SCP Bit 0 ACKB CKE0 Bit 0 MPBT Bit 0 SMIF SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 PWM TMR_0, TMR_1 BSC Module INT SYSTEM Rev. 1.00 Sep. 21, 2006 Page 597 of 658 REJ09B0310-0100 Section 23 List of Registers Register Abbreviation ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCR_X TCR_Y TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y TCNT_X TCNT_Y TCORC TCORA_X TCORB_X TCONRI TCONRS Bit 7 ICDR7 SVAX6 MLS SVA6 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit 7 CMIEB CMIEB CMFB CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 TMRX/Y Bit 6 ICDR6 SVAX5 WAIT SVA5 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit 6 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 5 ICDR5 SVAX4 CKS2 SVA4 AD7 AD7 AD7 AD7 ADST TME Bit 5 OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 4 ICDR4 SVAX3 CKS1 SVA3 AD6 AD6 AD6 AD6 SCAN PSS Bit 4 CCLR1 CCLR1 ICF ICIE Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 ICST Bit 3 ICDR3 SVAX2 CKS0 SVA2 AD5 AD5 AD5 AD5 CKS RST/NMI Bit 3 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 2 ICDR2 SVAX1 BC2 SVA1 AD4 AD4 AD4 AD4 CH2 CKS2 Bit 2 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 1 ICDR1 SVAX0 BC1 SVA0 AD3 AD3 AD3 AD3 CH1 CKS1 Bit 1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 0 ICDR0 FSX BC0 FS AD2 AD2 AD2 AD2 CH0 CKS0 Bit 0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 TMR_X, TMR_Y WDT_1 A/D Converter Module IIC_0 Rev. 1.00 Sep. 21, 2006 Page 598 of 658 REJ09B0310-0100 Section 23 List of Registers 23.3 Register States in Each Operating Mode HighSpeed/ Register Abbreviation TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 P6NCE P6NCMC P6NCCS P4NCE P4NCMC P4NCCS MSTPCRA MSTPCRB ICRD FCCS FPCS FECS FKEY Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized INT ROM SYSTEM PORT TCM_1 Module TCM_0 Rev. 1.00 Sep. 21, 2006 Page 599 of 658 REJ09B0310-0100 Section 23 List of Registers HighSpeed/ Register Abbreviation FMATS FTDAR TCRXY ICXR_0 ICXR_1 DDCSWR Reset Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized TMR_XY IIC_0 IIC_1 IIC_0, IIC_1 ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC PCSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWM, PWMX SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1 SYSTEM INT DTC INT Module ROM Rev. 1.00 Sep. 21, 2006 Page 600 of 658 REJ09B0310-0100 Section 23 List of Registers HighSpeed/ Register Abbreviation ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC OCRA OCRB TCR TOCR ICRA OCRAR ICRB OCRAF ICRC OCRDM ICRD DACR DADRA DACNT DADRB Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWMX FRT IIC_1 Module IIC_1 SCI_1 IIC_1 SCI_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Sep. 21, 2006 Page 601 of 658 REJ09B0310-0100 Section 23 List of Registers HighSpeed/ Register Abbreviation TCSR_0 TCNT_0 P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P7PIN IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_0, TMR_1 BSC INT SYSTEM PORT Module WDT_0 Rev. 1.00 Sep. 21, 2006 Page 602 of 658 REJ09B0310-0100 Section 23 List of Registers HighSpeed/ Register Abbreviation TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR15 to 0 SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWM Module TMR_0, TMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized A/D Converter IIC_0 SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Sep. 21, 2006 Page 603 of 658 REJ09B0310-0100 Section 23 List of Registers HighSpeed/ Register Abbreviation ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCR_X TCR_Y TCSR_X TCSR_Y TICRR TCORA_Y TICRF TCORB_Y TCNT_X TCNT_Y TCORC TCORA_X TCORB_X TCONRI TCONRS Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Hardware Standby Standby Module A/D Converter Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized WDT_1 TMR_X, TMR_Y Rev. 1.00 Sep. 21, 2006 Page 604 of 658 REJ09B0310-0100 Section 23 List of Registers 23.4 Register Selection Condition Register Abbreviation TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 P6NCE P6NCMC P6NCCS P4NCE P4NCMC P4NCCS MSTPCRA MSTPCRB ICRD FCCS FPCS FECS FKEY FMATS FTDAR No condition FLSHE = 1 INT ROM No condition SYSTEM No condition PORT MSTPB1 = 0 TCM_1 Register selection condition MSTPB0 = 0 Module TCM_0 Lower Address H'FBC0 H'FBC2 H'FBC4 H'FBC6 H'FBC8 H'FBC9 H'FBCA H'FBD0 H'FBD2 H'FBD4 H'FBD6 H'FBD8 H'FBD9 H'FBDA H'FE00 H'FE01 H'FE02 H'FE09 H'FE0A H'FE0B H'FE7E H'FE7F H'FE87 H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE Rev. 1.00 Sep. 21, 2006 Page 605 of 658 REJ09B0310-0100 Section 23 List of Registers Lower Address H'FEC6 H'FED4 H'FED5 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF82 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 Register Abbreviation TCRXY ICXR_0 ICXR_1 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC PCSR SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 Register selection condition MSTP8 = 0 MSTP4 = 0 MSTP3 = 0 MSTP4 = 0, IICE in STCR = 1 No condition Module TMR_XY IIC_0 IIC_1 IIC_0, IIC_1 INT No condition DTC No condition INT No condition FLSHE in STCR = 0 PWM, PWMX SYSTEM MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 MSTP6 = 0 SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 H'FF89 BRR_1 ICSR_1 H'FF8A H'FF8B SCR_1 TDR_1 Rev. 1.00 Sep. 21, 2006 Page 606 of 658 REJ09B0310-0100 Section 23 List of Registers Lower Address H'FF8C H'FF8D H'FF8E Register Abbreviation SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 Register selection condition MSTP6 = 0 Module SCI_1 MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 IIC_1 H'FF8F ICMR_1 SAR_1 H'FF90 H'FF91 H'FF92 H'FF94 TIER TCSR FRC OCRA OCRB MSTP13 = 0 FRT H'FF96 H'FF97 H'FF98 TCR TOCR ICRA OCRAR H'FF9A ICRB OCRAF H'FF9C ICRC OCRDM H'FF9E H'FEA0 ICRD DACR DADRAH MSTP11 = 0, MSTPA0 = 1 PWMX H'FEA1 H'FEA6 DADRAL DADRBH DACNTH H'FEA7 DADRBL DACNTL H'FFA8 TCSR_0 TCNT_0 (write) No condition WDT_0 H'FFA9 TCNT_0 (read) Rev. 1.00 Sep. 21, 2006 Page 607 of 658 REJ09B0310-0100 Section 23 List of Registers Lower Address H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBE H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 Register Abbreviation P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR P7PIN IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 Register selection condition No condition Module PORT No condition No condition INT SYSTEM No condition BSC MSTP12 = 0 TMR_0, TMR_1 Rev. 1.00 Sep. 21, 2006 Page 608 of 658 REJ09B0310-0100 Section 23 List of Registers Lower Address H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 Register Abbreviation PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR15 to 0 SMR_0 ICCR_0 Register selection condition MSTP11 = 0, MSTPA0 = 0 Module PWM MSTP7 = 0, IICE in STCR = 0 MSTP4 = 0, IICE in STCR = 1 MSTP7 = 0, IICE in STCR = 0 MSTP4 = 0, IICE in STCR = 1 MSTP7 = 0 SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 H'FFD9 BRR_0 ICSR_0 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 MSTP7 = 0, IICE in STCR = 0 MSTP4 = 0, IICE in STCR = 1 IIC_0 H'FFDF ICMR_0 SAR_0 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 (write) MSTP9 = 0 A/D Converter No condition WDT_1 H'FFEB TCNT_1 (read) Rev. 1.00 Sep. 21, 2006 Page 609 of 658 REJ09B0310-0100 Section 23 List of Registers Lower Address H'FFF0 Register Abbreviation TCR_X TCR_Y Register selection condition MSTP8 = 0 Module TMR_X, TMR_Y H'FFF1 TCSR_X TCSR_Y H'FFF2 TICRR TCORA_Y H'FFF3 TICRF TCORB_Y H'FFF4 TCNT_X TCNT_Y H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FFFE TCORC TCORA_X TCORB_X TCONRI TCONRS Rev. 1.00 Sep. 21, 2006 Page 610 of 658 REJ09B0310-0100 Section 23 List of Registers 23.5 Module INT INT INT INT INT INT INT INT INT INT INT INT BSC BSC DTC DTC DTC DTC DTC DTC PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Addresses (Classification by Type of Module) Number Register name of bits Address ICRD ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC IER BCR WSCR DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR P1PCR P1DDR P1DR P2PCR P2DDR P2DR P3PCR P3DDR P3DR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE87 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FFC2 H'FFC6 H'FFC7 H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FFAC H'FFB0 H'FFB2 H'FFAD H'FFB1 H'FFB3 H'FFAE H'FFB4 H'FFB6 Data Initial value width H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'D3 H'F3 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 611 of 658 REJ09B0310-0100 Section 23 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PWM PWM PWM PWM PWM PWM PWM PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX Number Register name of bits Address P4NCE P4NCMC P4NCCS P4DDR P4DR P5DR P5DDR P6NCE P6NCMC P6NCCS P6DR P6DDR P7PIN PWOERB PWOERA PWDPRB PWDPRA PWSL PWDR15 to 0 PCSR DACR DACR DADRAH DADRAH DADRAL DADRAL DACNTH DACNTH DADRBH DADRBH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE09 H'FE0A H'FE0B H'FFB5 H'FFB7 H'FFBA H'FFB8 H'FE00 H'FE01 H'FE02 H'FFBB H'FFB9 H'FFBE H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FF82 H'FEA0 H'FFA0 H'FEA0 H'FFA0 H'FEA1 H'FFA1 H'FEA6 H'FFA6 H'FEA6 H'FFA6 Data Initial value width H'00 H'00 H'00 H'40/H'00 H'00 H'F8 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'20 H'00 H'00 H'30 H'FF H'00 H'FF H'FF H'FF H'FF H'00 H'FF H'FF 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 612 of 658 REJ09B0310-0100 Section 23 List of Registers Module PWMX PWMX PWMX PWMX PWMX FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 Number Register name of bits Address DACNTL DACNTL DADRBL DADRBL PCSR TIER TCSR FRC OCRA OCRB TCR TOCR ICRA OCRAR ICRB OCRAF ICRC OCRDM ICRD TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16 16 8 8 16 16 16 16 16 8 H'FEA7 H'FFA7 H'FEA7 H'FFA7 H'FF82 H'FF90 H'FF91 H'FF92 H'FF94 H'FF94 H'FF96 H'FF97 H'FF98 H'FF98 H'FF9A H'FF9A H'FF9C H'FF9C H'FF9E H'FBC0 H'FBC2 H'FBC4 H'FBC6 H'FBC8 H'FBC9 H'FBCA H'FBD0 H'FBD2 H'FBD4 H'FBD6 H'FBD8 Data Initial value width H'03 H'03 H'FF H'FF H'00 H'01 H'00 H'0000 H'FFFF H'FFFF H'00 H'00 H'0000 H'FFFF H'0000 H'FFFF H'0000 H'0000 H'0000 H'0000 H'FFFF H'0000 H'00 H'00 H'00 H'0000 H'FFFF H'0000 H'00 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16 16 8 8 8 16 16 16 16 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 613 of 658 REJ09B0310-0100 Section 23 List of Registers Module TPU_1 TPU_1 TMR_0 TMR_0 TMR_0 TMR_0 TMR_0 TMR_1 TMR_1 TMR_1 TMR_1 TMR_1 TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y Number Register name of bits Address TCMCR_1 TCMIER_1 TCR_0 TCSR_0 TCORA_0 TCORB_0 TCNT_0 TCR_1 TCSR_1 TCORA_1 TCORB_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X TCORC TCORA_X TCORB_X TCONRI TCR_Y TCR_Y TCSR_Y TCSR_Y TCORA_Y TCORA_Y TCORB_Y TCORB_Y TCNT_Y TCNT_Y 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FBD9 H'FBDA H'FFC8 H'FFCA H'FFCC H'FFCE H'FFD0 H'FFC9 H'FFCB H'FFCD H'FFCF H'FFD1 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FEC8 H'FFF0 H'FEC9 H'FFF1 H'FECA H'FFF2 H'FECB H'FFF3 H'FECC H'FFF4 Data Initial value width H'00 H'00 H'00 H'00 H'FF H'FF H'00 H'00 H'FF H'FF H'FF H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'00 H'00 H'00 H'10 H'00 H'FF H'FF H'FF H'FF H'00 H'00 8 8 8 8 16 16 16 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 614 of 658 REJ09B0310-0100 Section 23 List of Registers Module Number Register name of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFFE H'FEC6 H'FFA8 (Write) H'FFA8 (Read) H'FFA8 (Write) H'FFA9 (Read) Data Initial value width H'00 H'00 H'00 H'00 H'00 H'00 8 8 16 8 16 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TMR_X, TMR_Y TCONRS TMR_XY WDT_0 WDT_0 WDT_0 WDT_0 WDT_1 WDT_1 WDT_1 WDT_1 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 TCRXY TCSR_0 TCSR_0 TCNT_0 TCNT_0 TCSR_1 TCSR_1 TCNT_1 TCNT_1 SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICXR_0 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 H'FFEA (Write) H'00 H'FFEA (Read) H'00 H'FFEA (Write) H'00 H'FFEB (Read) H'00 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FED4 H'FFD8 H'FFD9 H'FFDE H'FFDE H'FFDF H'FFDF H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'01 H'00 H'01 H'00 H'00 Rev. 1.00 Sep. 21, 2006 Page 615 of 658 REJ09B0310-0100 Section 23 List of Registers Module IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_0, IIC_1 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter ROM ROM ROM ROM ROM ROM Number Register name of bits Address ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 ICXR_1 ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 DDCSWR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR FCCS FPCS FECS FKEY FMATS FTDAR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FECE H'FECE H'FECF H'FECF H'FED0 H'FED1 H'FED5 H'FF88 H'FF89 H'FF8E H'FF8E H'FF8F H'FF8F H'FEE6 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE Data Initial value width H'01 H'00 H'00 H'01 H'00 H'00 H'01 H'00 H'01 H'00 H'00 H'0F H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'00 H'00 H'00 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 616 of 658 REJ09B0310-0100 Section 23 List of Registers Module SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM Number Register name of bits Address MSTPCRA MSTPCRB SBYCR LPWRCR MSTPCRH MSTPCRL STCR SYSCR MDCR 8 8 8 8 8 8 8 8 8 H'FE7E H'FE7F H'FF84 H'FF85 H'FF86 H'FF87 H'FFC3 H'FFC4 H'FFC5 Data Initial value width H'00 H'00 H'01 H'00 H'3F H'FF H'00 H'09 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 Rev. 1.00 Sep. 21, 2006 Page 617 of 658 REJ09B0310-0100 Section 23 List of Registers Rev. 1.00 Sep. 21, 2006 Page 618 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Power supply voltage* Input voltage (except port 7, P47, and P52) Input voltage (P47 and P52) Input voltage (port 7) Analog power supply voltage Analog input voltage Operating temperature Operating temperature (when flash memory is programmed or erased) Storage temperature Caution: Note: * Symbol VCC Vin Vin Vin AVCC VAN Topr Topr Tstg Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 -20 to +75 -20 to +75 -55 to +125 C Unit V Permanent damage to this LSI may result if absolute maximum ratings are exceeded. Make sure the applied power supply does not exceed 4.3V. Voltage applied to the VCC pin. The VCL pin should not be applied a voltage. Rev. 1.00 Sep. 21, 2006 Page 619 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.2 DC Characteristics Table 24.2 lists the DC characteristics. Table 24.3 lists the permissible output currents. Table 24.4 lists the bus drive characteristics. Table 24.2 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC*1 = 3.0 V to 3.6 V, VSS = AVSS*1 = 0 V Item Schmitt P67 to P60* and IRQ7 to (1) 3 trigger input IRQ0* voltage 2 Symbol Min. VT VT - Typ. Max. VCC x 0.7 VCC + 0.3 VCC + 0.3 AVCC + 0.3 5.5 VCC + 0.3 VCC x 0.1 VCC x 0.2 0.4 1.0 10.0 1.0 1.0 Unit V Test Conditions VCC x 0.2 - + V T - VT VIH + VCC x 0.05 VCC x 0.9 VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7 Input high voltage RES, STBY, NMI, MD2, MD1, MD0, and ETRST EXTAL Port 7 P47 and P52 (2) Input pins other than (1) and (2) above Input low voltage RES, STBY, MD2, MD1, MD0, and ETRST (3) VIL -0.3 -0.3 NMI, EXTAL, and input pins other than (1) and (3) above Output high voltage All output pins (except P47 and P52) P47 and P52* Output low voltage Input leakage current 4 VOH VCC- 0.5 VCC- 1.0 0.5 IOH = -200 A IOH = -1 mA IOH = -200 A IOL = 1.6 mA IOL = 5 mA A Vin = 0.5 to VCC - 0.5 V All output pins* RES 5 VOL Iin Ports 1, 2, and 3 STBY, NMI, MD2, MD1, and MD0 Port 7 Vin = 0.5 to AVCC - 0.5 V Rev. 1.00 Sep. 21, 2006 Page 620 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics Item Ports 1 to 6 Three-state leakage current (off state) Input pull-up MOS current Input capacitance Ports 1 to 3 All pins Symbol Min. Typ. Max. Unit Test Conditions ITSI 1.0 Vin = 0.5 to VCC - 0.5 V -IP Cin 5 150 15 pF Vin = 0 V Vin = 0 V f = 1MHz Ta = 25C VCC = 3.0 V to 3.6 V f = 20 MHz, all modules operating, high-speed mode VCC = 3.0 V to 3.6 V f = 20 MHz A Ta 50 C 50 C < Ta mA A V ms/V AVCC = 3.0 V to 3.6 V Supply current* 6 Normal operation ICC 20 30 mA Sleep mode Standby mode 14 10 2 20 40 80 4 Analog power supply current During A/D conversion AIcc A/D conversion standby 0.02 10 0 0.8 20 VCC start voltage VCC rising edge VCCSTART SVCC Notes: 1. Do not leave the AVCC and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a voltage in the range from 3.0 V to 3.6 V to the AVCC pin by connecting to the power supply (VCC). 2. Includes peripheral module inputs multiplexed on the pin. 3. IRQ2 includes the ADTRG input multiplexed on the pin. 4. P47 and P52 and the peripheral module outputs multiplexed on these pins are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0 and SCL1 (ICE bit in ICCR is 1). High levels of P47 and P52/SCK0 (ICE bit in ICCR is 0) are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from these pins when they are used as an output. 5. Indicates values when ICE = 0. Low level output when the bus drive function is selected is rated separately. 6. Supply current values are for VIH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. Rev. 1.00 Sep. 21, 2006 Page 621 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics Table 24.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, VSS = 0V Item Permissible output low current (per pin) SCL0 and SDA0 (bus drive function selected) Ports 1, 2, and 3 Other output pins Permissible output low current (total) Total of ports 1, 2, and 3 Total of all output pins, including the above -IOH -IOH IOL Symbol Min. IOL Typ. Max. 8 5 2 40 60 2 30 Unit mA Permissible output All output pins high current (per pin) Permissible output high current (total) Total of all output pins Notes: 1. To protect LSI reliability, do not exceed the output current values in table 24.3. 2. When driving a Darlington transistor or LED, always insert a current-limiting resistor in the output line, as show in figures 24.1 and 24.2. Table 24.4 Bus Drive Characteristics Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V Applicable Pins: SCL0, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT VT - + Min. VCC x 0.3 Typ. Max. VCC x 0.7 5.5 VCC x 0.3 0.5 0.4 10 1.0 Unit V Test Conditions VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL Cin ITSI + - VCC x 0.05 VCC x 0.7 - 0.5 IOL = 8 mA IOL = 3 mA pF A Vin = 0 V, f = 1 MHz, Ta = 25C Vin = 0.5 to VCC - 0.5 V Input capacitance Three-state leakage current (off state) Rev. 1.00 Sep. 21, 2006 Page 622 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics This LSI 2 k Port Darlington transistor Figure 24.1 Darlington Transistor Drive Circuit (Example) This LSI 600 Ports 1 to 3 LED Figure 24.2 LED Drive Circuit (Example) Rev. 1.00 Sep. 21, 2006 Page 623 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.3 AC Characteristics Figure 24.3 shows the test conditions for the AC characteristics. 3V C = 30pF : All ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level : 0.8 V * High level : 1.5 V RL LSI output pin C RH Figure 24.3 Output Load Circuit Rev. 1.00 Sep. 21, 2006 Page 624 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.3.1 Clock Timing Table 24.5 shows the clock timing. The clock timing specified here covers clock output () and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 21, Clock Pulse Generator. Table 24.5 Clock Timing Condition A: Condition B: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to 10 MHz VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to 20 MHz Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Reset oscillation stabilization (crystal) Symbol Min. tcyc tCH tCL tCr tCf tOSC1 100 30 30 20 8 Max. 125 20 20 Condition B Min. 50 20 20 20 8 Max. 125 5 5 ms Figure 24.5 Figure 24.6 Unit ns Reference Figure 24.4 Software standby tOSC2 oscillation stabilization time (crystal) External clock output stabilization delay time tDEXT 500 500 s Figure 24.5 tcyc tCH tCf tCL tCr Figure 24.4 System Clock Timing Rev. 1.00 Sep. 21, 2006 Page 625 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 24.5 Oscillation Stabilization Timing NMI IRQi (i = 0 to 7) tOSC2 Figure 24.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev. 1.00 Sep. 21, 2006 Page 626 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.3.2 Control Signal Timing Table 24.6 shows the control signal timing. Only external interrupts NMI, and IRQ0 to IRQ7 can be operated based on the subclock ( = 32.768 kHz). Table 24.6 Control Signal Timing Conditions: Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time (IRQ7 to IRQ0) IRQ hold time (IRQ7 to IRQ0) IRQ pulse width (IRQ7 to IRQ0) (exiting software standby mode) VCC = 3.0 V to 3.6 V, VSS = 0 V, = 32.768 kHz, 8 MHz to 20 MHz Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. Unit ns tcyc ns Figure 24.8 Test Conditions Figure 24.7 tRESS RES tRESW tRESS Figure 24.7 Reset Input Timing Rev. 1.00 Sep. 21, 2006 Page 627 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics tNMIS NMI tNMIW tNMIH IRQi (i = 0 to 7) tIRQS IRQ Edge input tIRQW tIRQH tIRQS IRQ Level input Figure 24.8 Interrupt Input Timing Rev. 1.00 Sep. 21, 2006 Page 628 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.3.3 Bus Timing Table 24.7 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock ( = 32.768 kHz). Table 24.7 Bus Timing Condition: Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to 20 MHz Symbol tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH Min. -- 0.5 x tcyc - 15 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0 10 30 5 Max. 20 -- -- 20 30 30 30 -- -- 1.0 x tcyc - 30 1.5 x tcyc - 25 2.0 x tcyc - 30 2.5 x tcyc - 25 3.0 x tcyc - 30 30 30 -- -- 30 -- -- -- -- Unit Test Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 24.9 to figure 24.13 Rev. 1.00 Sep. 21, 2006 Page 629 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics T1 T2 tAD A15 to A0, IOS* tCSD AS* tAS tAH tASD tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D7 to D0 (read) tRDS tRDH tWRD2 WR (write) tAS tWDD D7 to D0 (write) tWSW1 tWRD2 tAH tWDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.9 Basic Bus Timing (Two-State Access) Rev. 1.00 Sep. 21, 2006 Page 630 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics T1 T2 T3 tAD A15 to A0, IOS* tCSD AS* tAS tASD tASD tAH tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D7 to D0 (read) tRDS tRDH tWRD1 WR (write) tWDD tWDS D7 to D0 (write) tWSW2 tWRD2 tAH tWDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.10 Basic Bus Timing (Three-State Access) Rev. 1.00 Sep. 21, 2006 Page 631 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics T1 T2 TW T3 A15 to A0, IOS* AS* RD (read) D7 to D0 (read) WR (write) D7 to D0 (write) tWTS tWTH WAIT tWTS tWTH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.11 Basic Bus Timing (Three-State Access with One Wait State) Rev. 1.00 Sep. 21, 2006 Page 632 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics T1 T2 or T3 T1 T2 tAD A15 to A0, IOS* tAS AS* tASD tASD tAH tRSD2 RD (read) tACC3 D7 to D0 (read) tRDS tRDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.12 Burst ROM Access Timing (Two-State Access) Rev. 1.00 Sep. 21, 2006 Page 633 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics T1 T2 or T3 T1 tAD A15 to A0, IOS* AS* tRSD2 RD (read) tACC1 D7 to D0 (read) tRDS tRDH Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 24.13 Burst ROM Access Timing (One-State Access) Rev. 1.00 Sep. 21, 2006 Page 634 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.3.4 Timing of On-Chip Peripheral Modules Tables 24.8 and 24.9 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock ( = 32.768 kHz) are I/O ports, external interrupts (NMI, and IRQ0 to IRQ7), watchdog timer, and 8-bit timer (channels 0 and 1) only. Table 24.8 Timing of On-Chip Peripheral Modules Conditions: Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges TCM Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges PWM, PWMX Timer output delay time SCI Input clock cycle Asynchronous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS VCC = 3.0 V to 3.6 V, VSS = 0 V, = 32.768 kHz*, = 8 MHz to 20 MHz Symbol tPWD tPRS tPRH tFTOD tFTIS tFTCS tFTCWH tFTCWL tTCMIS tTCMCKS tTCMCKW tTMOD tTMRS tTMCS tTMCWH tTMCWL tPWOD tScyc Min. 30 30 30 30 1.5 2.5 30 30 1.5 30 30 1.5 2.5 4 6 0.4 50 50 30 Max. 50 50 50 50 0.6 1.5 1.5 50 ns Figure 24.25 ns Figure 24.24 tScyc tcyc ns tcyc Figure 24.22 Figure 24.23 tcyc tcyc ns Figure 24.19 Figure 24.21 Figure 24.20 ns Figure 24.17 Figure 24.18 tcyc Figure 24.16 ns Figure 24.15 Unit ns Test Conditions Figure 24.14 Note: * Applied only for the peripheral modules that are available during subclock operation. Rev. 1.00 Sep. 21, 2006 Page 635 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics T1 T2 tPRS Ports 1 to 7 (read) tPRH tPWD Ports 1 to 6 (write) Figure 24.14 I/O Port Input/Output Timing tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 24.15 FRT Input/Output Timing tFTCS FTCI tFTCWL tFTCWH Figure 24.16 FRT Clock Input Timing Rev. 1.00 Sep. 21, 2006 Page 636 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics tTCMIS TCMCYI0 TCMCYI1 Figure 24.17 TCM Input/Output Timing tTCMCKS TCMCKI0 TCMCKI1 tTCMCKW tTCMCKW tTCMCKS Figure 24.18 TCM Clock Input Timing tTMOD TMO_0, TMO_1 TMO_X, TMO_Y Figure 24.19 8-Bit Timer Output Timing tTMCS TMI_0, TMI_1 TMI_X, TMI_Y tTMCWL tTMCWH tTMCS Figure 24.20 8-Bit Timer Clock Input Timing Rev. 1.00 Sep. 21, 2006 Page 637 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics tTMRS TMI_0, TMI_1 TMI_X, TMI_Y Figure 24.21 8-Bit Timer Reset Input Timing tPWOD PW15 to PW0, PWX1 to PWX0 Figure 24.22 PWM, PWMX Output Timing tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 24.23 SCK Clock Input Timing SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS RxD0, RxD1 (receive data) tRXH Figure 24.24 SCI Input/Output Timing (Clock Synchronous Mode) Rev. 1.00 Sep. 21, 2006 Page 638 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics tTRGS ADTRG Figure 24.25 A/D Converter External Trigger Input Timing Table 24.9 I2C Bus Timing Conditions: Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA output fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: * VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to maximum operating frequency Symbol tSCL tSCLH tSCLL tSr tSf tOf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12 3 5 5 3 3 3 0.5 0 Typ. Max. 7.5* 300 250 1 400 ns pF tcyc ns Unit tcyc Test Conditions Figure 24.26 17.5 tcyc can be set according to the clock selected for use by the I2C module. Rev. 1.00 Sep. 21, 2006 Page 639 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics SDA0 SDA1 VIH VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0 SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 24.26 I2C Bus Interface Input/Output Timing Rev. 1.00 Sep. 21, 2006 Page 640 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics Table 24.10 H-UDI Timing Conditions: Item ETCK clock cycle time ETCK clock high pulse width ETCK clock low pulse width ETCK clock rise time ETCK clock fall time ETRST pulse width Reset hold transition pulse width ETMS setup time ETMS hold time ETDI setup time ETDI hold time ETDO data delay time Note: * When tcyc tTCKcyc VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to 20 MHz Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tRSTHW tTMSS tTMSH tTDIS tTDIH tTDOD Min. 50* 20 20 20 3 20 20 20 20 Max. 125* 5 5 20 ns Figure 24.29 tcyc Figure 24.28 Unit ns Test Conditions Figure 24.27 tTCKcyc tTCKH tTCKf ETCK tTCKL tTCKr Figure 24.27 ETCK Timing Rev. 1.00 Sep. 21, 2006 Page 641 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics ETCK RES tRSTHW ETRST tTRSTW Figure 24.28 Reset Hold Timing ETCK tTMSS tTMSH ETMS tTDIS tTDIH ETDI tTDOD ETDO Figure 24.29 H-UDI Input/Output Timing Rev. 1.00 Sep. 21, 2006 Page 642 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.4 A/D Conversion Characteristics Table 24.11 lists the A/D conversion characteristics. Table 24.11 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, = 8 MHz to 16 MHz VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, = 8 MHz to 20 MHz Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min. Typ. 10 8.38* 20 5 7.0 7.5 7.5 0.5 8.0 1 Condition B: Condition B Min. Typ. 10 13.4* 20 5 7.0 7.5 7.5 0.5 8.0 2 Max. Max. Unit Bits s pF k LSB Notes: 1. Value when using the maximum operating frequency in single mode of 134 states. 2. Value when using the maximum operating frequency in single mode of 266 states. Rev. 1.00 Sep. 21, 2006 Page 643 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.5 Flash Memory Characteristics Table 24.12 lists the flash memory characteristics. Table 24.12 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Ta = 0C to +75C (operating temperature range for programming/erasing) Symbol Min. 124 Item Programming time* * * Erase time* * * 124 Typ. 3 80 500 1000 10 10 20 3 Max. 30 800 5000 10000 30 30 60 Unit ms/128 bytes ms/4-Kbyte block ms/32-Kbyte block ms/64-Kbyte block s/512-Kbyte s/512-Kbyte s/512-Kbyte Times Years Test Conditions tP tE Programming time 124 (total)* * * Erase time (total)* * * 124 tP tE tPE NWEC tDRP 100* 10 Ta = 25C Ta = 25C Ta = 25C Programming and Erase 124 time (total)* * * Reprogramming count Data retention time* 4 Notes: 1. Programming and erase time depends on the data. 2. Programming and erase time do not include data transfer time. 3. This value indicates the minimum number of which the flash memory are reprogrammed with all characteristics guaranteed. (The guaranteed value ranges from 1 to the minimum number.) 4. This value indicates the characteristics while the flash memory is reprogrammed within the specified range (including the minimum number). Rev. 1.00 Sep. 21, 2006 Page 644 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics 24.6 Usage Notes It is necessary to connect a bypass capacitor between the VCC pin and VSS pin, and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 24.30. Vcc power supply External capacitor for internal step-down power stabilization One 0.1 F / 0.47 F or two in parallel VSS VSS Bypass capacitor VCC VCL 10 F 0.01 F It is recommended that a bypass capacitor be connected to the VCC pin. (The values are reference values.) When connecting, place a bypass capacitor near the pin. Do not connect Vcc power supply to the VCL pin. Always connect a capacitor for internal step-down power stabilization. Use one or two ceramic multilayer capacitor(s) (0.1 F / 0.47 F: connect in parallel when using two) and place it (them) near the pin. Figure 24.30 Connection of VCL Capacitor Rev. 1.00 Sep. 21, 2006 Page 645 of 658 REJ09B0310-0100 Section 24 Electrical Characteristics Rev. 1.00 Sep. 21, 2006 Page 646 of 658 REJ09B0310-0100 Appendix Appendix A. I/O Port States in Each Processing State I/O Port States in Each Processing State MCU Operating Mode 1 2, 3 (EXPE = 1) Hardware Software Standby Standby Mode Mode T Keep* Watch Mode Keep* Sleep Mode Keep* Subsleep Mode Keep* Subactive Mode A7 to A0 Address output/ input port I/O port L T T Keep* Keep* Keep* Keep* A15 to A8 Address output/ input port I/O port T T T T T T D7 to D0 Program Execution State A7 to A0 Address output/ input port I/O port A15 to A8 Address output/ input port I/O port D7 to D0 Table A.1 Port Name Pin Name Port 1 A7 to A0 Reset L T 2, 3 (EXPE = 0) Port 2 A15 to A8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 3 D7 to D0 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 47 WAIT 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 46 EXCL 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Ports 45 to 43 1 AS, WR, RD 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Ports 42 to 40 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 5 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) T T Keep Keep Keep Keep T T H T Keep Keep Keep Keep Keep Keep Keep Keep T Clock output Keep T T T/Keep Keep T/Keep Keep T/Keep Keep T/Keep I/O port WAIT/ I/O port I/O port EXCL input I/O port WAIT/ I/O port I/O port Clock output/ EXCL input/ input port AS, WR, RD I/O port I/O port Keep T Keep Keep Keep [DDR = 1] EXCL H input [DDR = 0] T H H T [DDR = 1] EXCL clock input output [DDR = 0] T H H AS, WR, RD I/O port I/O port I/O port I/O port Rev. 1.00 Sep. 21, 2006 Page 647 of 658 REJ09B0310-0100 Appendix MCU Operating Mode 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 7 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) T T T T T T I/O port I/O port Hardware Software Standby Standby Mode Mode T Keep Subsleep Mode Keep Program Execution State I/O port Port Name Pin Name Port 6 Reset T Watch Mode Keep Sleep Mode Keep Subactive Mode I/O port [Legend] H: High L: Low T: High-impedance state Keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up MOSs remain on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR used. DDR: Data direction register Note: * In the case of address output, the last address accessed is retained. Rev. 1.00 Sep. 21, 2006 Page 648 of 658 REJ09B0310-0100 Appendix B. Product Codes Product Code F-ZTAT Version R4F2125 Mark Code F2125VPS20 F2125VFA20 F2125VTF20 PROM (OTP Version) R4P2125 Package (Package Code) PRDP0064BB-A (DP-64S) PRQP0064GB-A (FP-64A) PTQP0080KC-A (TFP-80C) Product Type H8S/2125 P2125VPS20 PRDP0064BB-A (DP-64S) Rev. 1.00 Sep. 21, 2006 Page 649 of 658 REJ09B0310-0100 C. Appendix 1 b3 32 Z A1 A E L REJ09B0310-0100 RENESAS Code PRDP0064BB-A Previous Code DP-64S/DP-64SV MASS[Typ.] 8.8g D JEITA Package Code P-SDIP64-17x57.6-1.78 Package Dimensions Rev. 1.00 Sep. 21, 2006 Page 650 of 658 33 Reference Symbol 64 Dimension in Millimeters Min e1 Nom 19.05 Max Figure C.1 Package Dimensions (SDIP-64) bp e e1 c D E A A1 bp b3 c 0.20 0.51 0.38 57.6 17.0 58.5 18.6 5.08 0.48 1.0 0.25 0.58 0.36 e Z L 0 1.53 1.78 15 2.03 1.46 2.54 JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GB-A Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g HD *1 D 33 48 49 bp b1 32 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 E *2 HE Terminal cross section ZE c Reference Symbol Dimension in Millimeters 17 Min 64 1 F 16 A A2 ZD c A1 Figure C.2 Package Dimensions (QFP-64) L L1 Detail F *3 e y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 16.9 17.2 17.5 16.9 17.2 17.5 3.05 0.00 0.10 0.25 0.29 0.37 0.45 0.35 0.12 0.17 0.22 0.15 0 8 0.8 0.15 0.10 1.0 1.0 0.5 0.8 1.1 1.6 Appendix Rev. 1.00 Sep. 21, 2006 Page 651 of 658 REJ09B0310-0100 Appendix c1 E *2 HE c 1 Index mark F 20 A A2 ZE ZD c Figure C.3 Package Dimensions (TQFP-80) A1 REJ09B0310-0100 RENESAS Code PTQP0080KC-A Previous Code TFP-80C/TFP-80CV MASS[Typ.] 0.4g HD *1 JEITA Package Code P-TQFP80-12x12-0.50 D 41 60 61 40 bp b1 Rev. 1.00 Sep. 21, 2006 Page 652 of 658 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Terminal cross section 21 Reference Symbol Dimension in Millimeters Min 80 L L1 *3 e y bp x M Detail F D E A2 HD H1 A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.10 0.10 1.25 1.25 0.4 0.5 0.6 1.0 Index Numerics 14-bit PWM timer (PWMX)................... 197 16-bit count mode................................... 290 16-bit cycle measurement timer (TCM)..................................................... 243 8-bit PWM timer (PWM)........................ 183 8-bit timer (TMR) ................................... 267 C Cascaded connection............................... 290 Chain transfer.......................................... 140 Clock pulse generator ............................. 553 Clocked synchronous mode .................... 348 CMIA ...................................................... 294 CMIAY ................................................... 294 CMIB ...................................................... 294 CMIBY ................................................... 294 Communications protocol ....................... 521 Compare-match count mode ................... 290 Condition field .......................................... 45 Condition-code register............................. 28 Conversion cycle..................................... 207 Crystal resonator ..................................... 554 A A/D conversion time............................... 446 A/D converter ......................................... 439 Absolute address....................................... 47 Activation by interrupt............................ 144 Activation by software............................ 144 Address map ............................................. 64 Address space ........................................... 24 Addressing modes..................................... 46 ADI interrupt .......................................... 449 Arithmetic operations instructions............ 36 D Data transfer controller (DTC)................ 125 Data transfer instructions .......................... 35 DDCSWI................................................. 425 Direct transitions..................................... 582 Download pass/fail result parameter....... 476 DTC vector table..................................... 134 B Bcc............................................................ 28 Bit manipulation instructions.................... 40 Bit rate .................................................... 325 Block data transfer instructions ................ 44 Block transfer mode................................ 139 Boot mode .............................................. 486 Branch instructions ................................... 42 Break....................................................... 358 Burst ROM interface............................... 120 Bus arbitration ........................................ 123 E EEPMOV instruction ................................ 55 Effective address....................................... 50 Effective address extension....................... 45 ERI.......................................................... 357 Error protection....................................... 515 Exception handling ................................... 67 Exception handling vector table................ 68 Extended control register .......................... 27 External clock ......................................... 555 External trigger ....................................... 448 Rev. 1.00 Sep. 21, 2006 Page 653 of 658 REJ09B0310-0100 F Flash erase block select parameter ......... 483 Flash MAT configuration ....................... 461 Flash memory ......................................... 457 Flash multipurpose data destination area parameter ........................................ 480 Flash pass/fail result parameter .............. 484 Flash programming/erasing frequency control parameter.................................... 478 Formatless............................................... 385 Framing error.......................................... 338 Interrupt exception handling vector table................................................ 85 Interrupt mask bit...................................... 28 Interval timer mode................................. 310 L List of registers ....................................... 585 Logic operations instructions.................... 38 LSI internal states in each operating mode ....................................... 572 G General registers ....................................... 26 M Mark state ............................................... 358 MDCR..................................................... 549 Medium-speed mode............................... 574 Memory indirect ....................................... 49 Mode comparison ................................... 460 Mode transition diagram ......................... 571 Module stop mode .................................. 582 Multiprocessor communication function ................................................... 342 H Hardware protection ............................... 514 Hardware standby mode ......................... 578 I I2C bus data format ................................. 394 I2C bus interface (IIC) ............................ 365 ICIA........................................................ 236 ICIB ........................................................ 236 ICIC ........................................................ 236 ICID........................................................ 236 ICIX........................................................ 294 Idle cycle ................................................ 121 IICI ......................................................... 425 Immediate ................................................. 48 Input capture........................................... 230 Input capture operation........................... 292 Instruction set ........................................... 33 Internal block diagram................................ 3 Interrupt controller.................................... 75 Interrupt exception handling..................... 71 N Noise Canceler........................................ 423 Normal mode ............................ 20, 137, 145 Number of DTC execution states............ 143 O OCIA....................................................... 236 OCIB....................................................... 236 On-board programming .......................... 486 On-board programming mode................. 457 Operation field .......................................... 45 Output compare....................................... 229 Overflow ................................................. 308 Rev. 1.00 Sep. 21, 2006 Page 654 of 658 REJ09B0310-0100 Overrun error .......................................... 338 OVI ......................................................... 294 OVIY ...................................................... 294 P Parity error.............................................. 338 Pin arrangement.......................................... 4 Pin functions ............................................. 11 Power-down modes ................................ 563 Procedure program ................................. 505 Program counter ....................................... 27 Program-counter relative .......................... 48 Programmer mode .................................. 518 Programming/erasing interface parameter ................................................ 475 Programming/erasing interface register .................................................... 468 Protection................................................ 514 R RAM ....................................................... 455 Register field............................................. 45 Register indirect........................................ 46 Register indirect with displacement.......... 47 Register indirect with post-increment....... 47 Register indirect with pre-decrement........ 47 Register selection condition.................... 605 Register states in each operating mode ....................................... 599 Registers ABRKCR.............................................. 79 ADCR ................................................. 444 ADCSR............................................... 443 ADDR................................................. 442 BAR...................................................... 80 BCR .................................................... 107 BRR .................................................... 325 CRA.................................................... 130 CRB .................................................... 130 DACNT............................................... 199 DACR ................................................. 202 DADR ................................................. 200 DAR.................................................... 130 DDCSWR ........................................... 389 DTCER ............................................... 131 DTVECR ............................................ 132 FCCS................................................... 468 FECS................................................... 471 FKEY .................................................. 472 FMATS ............................................... 473 FPCS ................................................... 471 FRC..................................................... 218 FTDAR ............................................... 474 ICCR ................................................... 375 ICDR................................................... 368 ICMR .................................................. 372 ICR................................................ 78, 218 ICSR.................................................... 384 ICXR................................................... 390 IER........................................................ 82 ISR ........................................................ 82 LPWRCR ............................................ 566 MDCR................................................... 58 MRA ................................................... 128 MRB.................................................... 129 MSTPCR............................................. 568 OCRA ................................................. 218 OCRAF ............................................... 219 OCRAR............................................... 219 OCRDM.............................................. 219 P1DDR................................................ 152 P1DR................................................... 153 P1PCR................................................. 153 P2DDR................................................ 156 P2DR................................................... 157 P2PCR................................................. 157 P3DDR................................................ 162 P3DR................................................... 163 Rev. 1.00 Sep. 21, 2006 Page 655 of 658 REJ09B0310-0100 P3PCR ................................................ 163 P4DDR ............................................... 166 P4DR .................................................. 167 P4NCCS ............................................. 169 P4NCE................................................ 168 P4NCMC ............................................ 168 P5DDR ............................................... 172 P5DR .................................................. 172 P6DDR ............................................... 174 P6DR .................................................. 175 P6NCCS ............................................. 176 P6NCE................................................ 175 P6NCMC ............................................ 176 P7PIN ................................................. 181 PCSR .................................................. 191 PWDPR .............................................. 189 PWDR ................................................ 188 PWOER .............................................. 190 PWSL ................................................. 186 RDR.................................................... 318 RSR .................................................... 318 SAR .................................................... 369 SARX ................................................. 370 SBYCR............................................... 564 SCMR................................................. 324 SCR .................................................... 320 SMR.................................................... 319 SSR..................................................... 322 STCR .................................................... 60 SYSCR ................................................. 59 TCMCNT ........................................... 246 TCMCR .............................................. 249 TCMCSR............................................ 247 TCMICR............................................. 247 TCMICRF........................................... 247 TCMIER ............................................. 251 TCMMLCM ....................................... 246 TCNT.......................................... 272, 303 TCONRI ............................................. 283 TCONRS ............................................ 283 Rev. 1.00 Sep. 21, 2006 Page 656 of 658 REJ09B0310-0100 TCOR.................................................. 272 TCR............................................. 224, 273 TCSR .......................................... 221, 277 TDR .................................................... 318 TICRF ................................................. 282 TICRR................................................. 282 TIER ................................................... 220 TOCR.................................................. 225 TSR ..................................................... 318 WSCR ................................................. 108 Repeat mode ........................................... 138 Reset ......................................................... 69 Reset exception handling .......................... 69 Resolution ............................................... 197 RXI ......................................................... 357 S Scan mode............................................... 445 Serial communication interface (SCI)..... 315 Serial communication interface specifications .......................................... 519 Serial formats.......................................... 394 Shift instructions ....................................... 39 Single mode ............................................ 445 Sleep mode.............................................. 575 Software protection................................. 515 Software standby mode........................... 576 Speed measurement mode....................... 256 Stack pointer ............................................. 26 Stack status ............................................... 72 Subactive mode....................................... 581 Subsleep mode ........................................ 580 SWDTEND............................................. 132 System control instructions....................... 43 T TCORC ................................................... 282 TEI .......................................................... 357 Trap instruction exception handling ......... 71 TRAPA instruction ................................... 71 TXI ......................................................... 357 V Vector number for the software activation interrupt .................................. 132 U User boot MAT....................................... 517 User boot memory MAT ........................ 457 User boot mode....................................... 501 User MAT....................................... 457, 517 User program mode ................................ 490 W Wait Control ........................................... 118 Watch mode ............................................ 579 Watchdog timer (WDT) .......................... 301 Watchdog timer mode............................. 308 WOVI...................................................... 311 Rev. 1.00 Sep. 21, 2006 Page 657 of 658 REJ09B0310-0100 Rev. 1.00 Sep. 21, 2006 Page 658 of 658 REJ09B0310-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2125 Group Publication Date: Rev.1.00, Sep. 21, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8S/2125 Group Hardware Manual |
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